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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004, zarlink semiconductor inc. all rights reserved. features ? 4096 channel x 4096 channel non-blocking digital time division multiplex (tdm) switch at 8.192 mbps and 16.384 mbps or using a combination of ports running at 2.048 mbps, 4.096 mbps, 8.192 mbps and 16.384 mbps ? 32 serial tdm input, 32 serial tdm output streams ? output streams can be configured as bi- directional for connection to backplanes ? exceptional input clock cy cle to cycle variation tolerance (20 ns for all rates) ? per-stream input and output data rate conversion selection at 2.048 mbps, 4.096 mbps 8.192 mbps or 16.384 mbps. input and output data rates can differ ? per-stream high impedance control outputs (stohz) for 16 output streams ? per-stream input bit delay with flexible sampling point selection ? per-stream output bit and fractional bit advancement ? per-channel itu-t g.711 pcm a-law/ -law translation ? four frame pulse and four reference clock outputs ? three programmable delayed frame pulse outputs ? input clock: 4.096 mhz, 8.192 mhz, 16.384 mhz ? input frame pulses: 61 ns, 122 ns, 244 ns ? per-channel constant or variable throughput delay for frame integrity and low latency applications february 2004 ordering information ZL50023gac 256-ball pbga ZL50023qcc 256-lead lqfp -40 c to +85 c ZL50023 enhanced 4 k digital switch data sheet figure 1 - ZL50023 functional block diagram data memory internal registers & microprocessor interface input timing output hiz te s t p o r t control s/p converter stohz[15:0] fpo[3:0] cko[3:0] stio[31:0] ode reset v ss v dd_io v dd_core fpi cki connection memory mot_intel ds _rd cs d[15:0] a[13:0] tms tdi tdo tck trst output timing sti[31:0] fpo_off[2:0] p/s converter dta _rdy r/w _wr
ZL50023 data sheet 2 zarlink semiconductor inc. ? per stream (32) bit error rate test circuits complying to itu-o.151 ? per-channel high impedance output control ? per-channel message mode ? control interface compatible with intel and motorola 16-bit non-multiplexed buses ? connection memory block programming ? supports st-bus and gci-bus standards for input and output timing ? ieee-1149.1 (jtag) test port ? 3.3 v i/o with 5 v tolerant inputs; 1.8 v core voltage applications ? pbx and ip-pbx ? small and medium digital switching platforms ? remote access servers and concentrators ? wireless base stations and controllers ? multi service access platforms ? digital loop carriers ? computer telephony integration description the ZL50023 is a maximum 4096 x 4096 ch annel non-blocking digital time divisi on multiplex (tdm) switch. it has thirty-two input streams (sti0 - 31) and thirty-two output streams (stio0 - 31). the device can switch 64 kbps and nx64 kbps tdm channels from any input stream to any output stream. each of the input and output streams can be independently programmed to operate at any of the following data rates: 2.048 mbps, 4.096 mbps, 8.192 mbps or 16.384 mbps. the ZL50023 provides up to sixteen high impedance control outputs (stohz0 - 15) to support the use of external tristate drivers for the first sixtee n output streams (stio0 - 15) . the output streams can be configured to operate in bi-directional m ode, in which case sti0 - 31 will be ignored. the device contains two types of internal memory - dat a memory and connection memory. there are four modes of operation - connection mode, message mode, ber mode and high impedance mode. in connection mode, the contents of the connection memory define, for each ou tput stream and channel, the source stream and channel (the actual data to be output is stored in the data memory ). in message mode, the connection memory is used for the storage of microprocessor data. using zarlink' s message mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. this feature is useful for transferring control and status information for external circuits or other tdm devices. in ber mode the output channel data is replaced with a pseudorandom bit sequence (prbs) from one of 32 prbs generators that generates a 2 15 -1 pattern. on the input side channels can be routed to one of 32 bit erro r detectors. in high impedance mode the selected output channel can be put into a high impedance state. the configurable non-multiplexed micr oprocessor port allows users to program various device operating modes and switching configurations. users ca n employ the microprocessor port to pe rform register read/ write, connection memory read/write, and data memory r ead operations. the port is configurable to interface with either motorola or intel-type microprocessors. the device also supports the mandatory requirements of the ieee-1149.1 (jtag) st andard via the test port.
ZL50023 data sheet table of contents 3 zarlink semiconductor inc. 1.0 pinout diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 bga pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 qfp pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.0 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.0 data rates and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 external high impedance control, stohz0 - 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 input clock (cki) and input frame pulse (fpi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.0 st-bus and gci-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.0 output timing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.0 data input delay and data output advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 input bit delay programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 input bit sampling point programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 output advancement programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.4 fractional output bit advancement programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 external high impedance control advancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.0 data delay through the switching paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1 variable delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2 constant delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.0 connection memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.0 connection memory block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.1 memory block programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.0 device performance divided clock and multiplied clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.1 divided clock mode performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.2 multiplied clock mode performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12.0 microprocessor port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.0 device reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 13.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 13.2 device initialization on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 13.3 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14.0 pseudorandom bit generation and error detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 15.0 pcm a-law/m-law translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 16.0 quadrant frame programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 17.0 jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 17.1 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 17.2 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 17.3 test data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 17.4 bsdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 18.0 register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 19.0 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 20.0 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 20.1 memory address mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 20.2 connection memory low (cm_l) bit assi gnment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 20.3 connection memory high (cm_h) bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 21.0 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 22.0 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ZL50023 data sheet list of figures 4 zarlink semiconductor inc. figure 1 - ZL50023 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - ZL50023 256-ball 17 mm x 17 mm pbga (as viewed through top of package) . . . . . . . . . . . . . . . . . . . 6 figure 3 - ZL50023 256-lead 28 mm x 28 mm lqfp (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4 - input timing when ckin1 - 0 bits = ?10? in the cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5 - input timing when ckin1 - 0 bits = ?01? in the cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6 - input timing when ckin1 - 0 = ?00? in the cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7 - output timing for cko0 and fpo0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8 - output timing for cko1 and fpo1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9 - output timing for cko2 and fpo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10 - output timing for cko3 and fpo3 with ck0fpo3sel1-0= ?11? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 figure 11 - input bit delay timing diagram (st-bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12 - input bit sampling point programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 13 - input bit delay and factional sampling point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14 - output bit advancement timing diagram (st-bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15 - output fractional bit advancement timing diagram (st-bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 16 - channel switching external high impedance control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 17 - data throughput delay for variable delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18 - data throughput delay for constant delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 19 - timing parameter measurement voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 20 - motorola non-multiplexed bus timing - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 21 - motorola non-multiplexed bus timing - write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 22 - intel non-multiplexed bus timing - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 23 - intel non-multiplexed bus timing - write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 24 - jtag test port timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 25 - frame pulse input and clock input timing diagram (st-bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 26 - frame pulse input and clock input timing diagram (gci-bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 27 - st-bus input timing diagram when operated at 2 mbps, 4 mbps, 8 mbps. . . . . . . . . . . . . . . . . . . . 65 figure 28 - st-bus input timing diagram when operated at 16 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 29 - gci-bus input timing diagra m when operated at 2 mbps, 4 mbps, 8 mbps . . . . . . . . . . . . . . . . . . . 66 figure 30 - gci-bus input timing diagram when operated at 16 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 31 - st-bus output timing diagram when operated at 2, 4, 8 or 16 mbps . . . . . . . . . . . . . . . . . . . . . . . 68 figure 32 - gci-bus output timing diagra m when operated at 2, 4, 8 or 16 mbps . . . . . . . . . . . . . . . . . . . . . . . 69 figure 33 - serial output and external control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 34 - output drive enable (ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 35 - input and output frame boundary offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 36 - fpo0/3 and cko0/3 timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 37 - fpo1/3 and cko1/3 timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 38 - fpo2/3 and cko2/3 timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 39 - fpo3 and cko3 timing diagram (32.768 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 40 - output timing (st-bus format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ZL50023 data sheet list of tables 5 zarlink semiconductor inc. table 1 - cki and fpi configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 2 - cki and fpi configurations for divided clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3 - cki and fpi configurations for multiplied clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4 - output timing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5 - delay for variable delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6 - connection memory low after block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7 - connection memory high after block programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8 - generated output frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9 - input and output voice and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10 - definition of the four quadrant frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11 - quadrant frame bit replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12 - address map for registers (a13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 13 - control register (cr) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 14 - internal mode selection register (ims) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 15 - software reset register (srr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 16 - output clock and frame pulse cont rol register (ocfcr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17 - output clock and frame pulse sele ction register (ocfsr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18 - fpo_off[n] register (fpo_off[n]) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 19 - internal flag register (ifr) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 20 - ber error flag register 0 (berfr0) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 21 - ber error flag register 1 (berfr1) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 22 - ber receiver lock register 2 (berlr2) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 23 - ber receiver lock register 3 (berlr3) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24 - stream input control register 0 - 31 (sicr0 - 31) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 25 - stream input quadrant frame regi ster 0 - 31 (siqfr0 - 31) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 26 - stream output control register 0 - 31 (socr0 - 31) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 27 - ber receiver start register [n] (brsr[n]) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 28 - ber receiver length register [n] (brlr[n]) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 29 - ber receiver control register [n] (brcr[n]) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 30 - ber receiver error register [n] (brer[n]) bits - read only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 31 - address map for memory locations (a13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 32 - connection memory low (cm_l) bit assignment when cmm = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 33 - connection memory low (cm_l) bit assignment when cmm = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 34 - connection memory high (cm_h) bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ZL50023 data sheet 6 zarlink semiconductor inc. 1.0 pinout diagrams 1.1 bga pinout figure 2 - ZL50023 256-ball 17 mm x 17 mm pbga (as viewed through top of package) 12345678 910111213141516 a v ss sti29 sti28 sti27 sti25 sti26 sti24 nc nc stio22 stio23 stio21 stio20 nc nc v ss a b sti31 sti10 sti5 sti4 cko2 sti0 cko0 nc v dd_ core fpi cki ic_open ic_open ic_gnd ode stio19 b c sti30 sti9 v ss sti7 sti6 sti1 cko1 nc v ss ic_open ic_open ic_open ic_gnd v ss stio15 stio18 c d sti17 sti11 v dd_io sti3 sti2 nc nc nc nc v ss fpo_ off1 ic_gnd stio13 v dd_io stio14 stio16 d e sti16 sti14 sti8 v dd_io v ss v dd_ core nc nc nc nc v dd_ core v ss v dd_io stio12 fpo2 stio17 e f sti19 sti15 sti12 sti13 v dd_io v dd_ core v dd_ core v ss v ss v dd_ core v dd_ core v dd_io ic_open fpo3 fpo_ off2 stohz15 f g sti18 reset ic_gnd ic_open tdo v dd_io v ss v ss v ss v ss v dd_io a12 a13 fpo1 fpo0 stohz14 g h sti21 v ss v ss v dd_ core nc v ss v ss v ss v ss v ss a7 a9 a10 fpo_ off0 a11 stohz12 h j sti20 v dd_io v dd_io v ss v ss cko3 v ss v ss v ss v ss a3 a4 a5 a8 a6 stohz13 j k sti22 v ss tms v ss v dd_ core v dd_io v ss v ss v ss v ss v dd_io ic_open a0 a2 a1 stohz11 k l sti23 v dd_ core trst tck v dd_io v dd_ core v dd_ core v ss v ss v dd_ core v dd_ core v dd_io stio10 stio11 stio9 stohz10 l m stio25 nc tdi d0 v ss v dd_ core v dd_ core d6 d10 v dd_ core v dd_ core v ss mot _intel ic_open stio8 stohz9 m n stio24 nc v dd_io stio0 stohz3 d1 d5 d7 d11 d13 r/w _wr dta _ rdy stio4 v dd_io stohz5 stohz8 n p stio26 nc v ss stio1 stio3 stohz1 d3 d8 d14 nc stio5 stohz4 stohz6 v ss stohz7 nc p r stio27 nc stohz0 stio2 stohz2 d2 d4 d9 d12 d15 cs ds _rd ic_open stio6 stio7 nc r t v ss stio28 stio29 stio31 stio30 nc nc nc nc nc nc nc nc nc nc v ss t 12345678 910111213141516 note: a1 corner id entified by metallized marking. note: pinout is shown as viewed through top of package.
ZL50023 data sheet 7 zarlink semiconductor inc. 1.2 qfp pinout figure 3 - ZL50023 256-lead 28 mm x 28 mm lqfp (top view) 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 22 24 26 28 30 20 18 16 14 12 10 8 6 4 2 120 102 104 106 108 110 114 116 118 112 52 54 56 58 60 50 48 46 44 42 40 38 36 34 32 100 82 84 86 88 90 94 96 98 92 80 66 68 70 74 76 78 72 132 134 136 138 140 142 144 146 148 150 cki fpi ic_open ic_open ic_open ic_open ic_open ic_gnd vdd_io vss ic_gnd ode vdd_io stio_23 stio_22 stio_21 stio_20 62 64 122 124 126 128 182 184 186 188 190 sti25 sti24 vss vdd_io sti_7 sti_6 sti_3 sti_2 sti_1 sti_0 nc vss nc nc nc nc nc nc vss sti27 sti26 sti_5 sti_4 vdd_io cko2 cko1 vss vdd_core cko0 vss vdd_io nc nc vss vdd_core sti_22 vdd_io sti_23 sti_21 sti_20 sti_19 sti_18 sti_17 vdd_io trst tck tms vss vdd_core vss vdd_core vss vss cko3 vdd_io vdd_core vss vss nc vdd_io vss vdd_core vss vss vdd_core tdo reset ic_open ic_gnd vss vdd_io sti_15 sti_14 sti_11 sti_10 sti_9 sti_8 sti30 sti31 sti_16 vss tdi sti29 vdd_io sti28 202 220 218 216 214 212 208 206 204 210 222 240 238 236 234 232 228 226 224 230 242 256 254 252 248 246 244 250 200 198 196 194 vss sti_13 sti_12 stio_28 stio_29 stio_30 stio_31 vdd_io vss stio_0 stio_1 stio_2 stio_3 stohz_0 stohz_1 stohz_2 stohz_3 vdd_io vss d0 vdd_core vss d1 d2 d3 d4 d5 d7 d8 d9 d6 vdd_io vss d10 vdd_core vss d11 d12 d13 d14 d15 r/w _wr cs mot_intel ds _rd nc dta _rdy ic_open vdd_core vss ic_open vdd_io vss stio_4 stio_5 stio_6 stio_7 stohz_4 stohz_5 stohz_6 stohz_7 vdd_io vss nc nc nc nc nc vdd_io vss stio_8 stio_9 stio_10 stio_11 stohz_8 stohz_9 stohz_10 stohz_11 vdd_io ic_open vss vdd_core vss a0 a1 a2 a3 a4 a7 a6 a5 a11 a10 a9 a8 vdd_core vss a13 a12 ic_open vdd_io vss fpo_off0 fpo0 fpo_off1 fpo1 fpo2 fpo_off2 fpo3 vdd_core vss ic_gnd vdd_io vss stio_12 stio_13 stio_14 stio_15 stohz_12 stohz_13 stohz_14 stohz_15 vdd_io vss stio_16 stio_17 stio_18 stio_19 nc nc nc nc nc nc nc vss vdd_core vss vss vdd_io stio_27 stio_24 stio_25 stio_26 vss nc nc nc 192 130 nc nc nc nc nc nc
ZL50023 data sheet 8 zarlink semiconductor inc. 2.0 pin description pbga pin number lqfp pin number pin name description b9, e6, e11, f6, f7, f10, f11, h4, k5, l2, l6, l7, l10, l11, m6, m7, m10, m11 19, 33, 45, 83, 95, 109, 146, 157, 173, 213, 217, 224, 231, 233 v dd_core power supply for the core logic: +1.8 v d3, d14, e4, e13, f5, f12, g6, g11, j2, j3, k6, k11, l5, l12, n3, n14 5, 15, 29, 49, 57, 69, 79, 101, 113, 121, 133, 143, 160, 169, 177, 186, 195, 207, 220, 226, 241, 249 v dd_io power supply for i/o: +3.3 v a1, a16, c3, c9, c14, d10, e5, e12, f8, f9, g7, g8, g9, g10, h2, h3, h6, h7, h8, h9, h10, j4, j5, j7, j8, j9, j10, k2, k4, k7, k8, k9, k10, l8, l9, m5, m12, p3, p14, t1, t16 8, 17, 21, 31, 35, 47, 50, 60, 71, 81, 85, 97, 103, 111, 114, 123, 142, 145, 147, 156, 158, 162, 171, 175, 178, 188, 199, 209, 214, 216, 218, 222, 223, 228, 230, 232, 235, 242, 251 v ss ground k3 234 tms test mode select (5 v-tolerant input with internal pull-up) jtag signal that controls the stat e transitions of the tap controller. this pin is pulled high by an internal pull-up resistor when it is not driven.
ZL50023 data sheet 9 zarlink semiconductor inc. l4 238 tck test clock (5 v-tolerant schmitt- triggered input with internal pull-up) provides the clock to the jtag test logic. l3 239 trst test reset (5 v-tolerant input with internal pull-up) asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low during power-up to ensure that the devi ce is in the normal functional mode. when jtag is not being used, this pin should be pulled low during normal operation. m3 240 tdi test serial data in (5 v-tolerant input with internal pull-up) jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an internal pull-up resistor when it is not driven. g5 212 tdo test serial data out (5 v- tolerant three-state output) jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag is not enabled. b12, b13, c10, c11, c12, f13, g4, k12, m14, r13 46, 48, 80, 105, 149, 150, 151, 152, 153, 210 ic_open internal test mode (5 v-tolerant input with internal pull-down) these pins may be left unconnected. g3, d12, b14,c13 144, 107, 148, 208 ic_gnd internal test mode enable (5 v-tolerant input) these pins must be low. a8, a9, a14, a15, e10, m2, n2, p2, p16, r2, r16, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, d9, e8, c8, e7, d6, h5,p10, e9, d8, b8, d7, 61, 62, 63, 64, 65, 66, 67, 68, 134, 135, 136, 137, 138, 139, 140, 215, 219, 225, 229, 236, 237159, 163, 165, 167, 176, 221,43, 161, 164, 166, 168 nc no connect these pins must be left unconnected. pbga pin number lqfp pin number pin name description
ZL50023 data sheet 10 zarlink semiconductor inc. g15, g14, e15, f14 102, 106, 110, 112 fpo0 - 3 st-bus/gci-bus frame pulse outputs 0 to 3 (5 v-tolerant three-state outputs) fpo0: 8 khz frame pulse corres ponding to the 4.096 mhz output clock of cko0. fpo1: 8 khz frame pulse corres ponding to the 8.192 mhz output clock of cko1. fpo2: 8 khz frame pulse corresponding to 16.384 mhz output clock of cko2. fpo3: programmable 8 khz fr ame pulse corresponding to 4.096 mhz, 8.192 mhz, 16.384 mhz , or 32.768 mhz output clock of cko3. h14, d11, f15 100, 104, 108 fpo_off0 - 2 generated offset frame pulse outputs 0 to 2 (5 v-tolerant three-state outputs) individually programmable 8 khz frame pulses, offset from the output frame boundary by a programmable number of channels. b7, c7, b5, j6 170, 172, 174, 227 cko0 - 3 st-bus/gci-bus clock outputs 0 to 3 (5 v-tolerant three-state outputs) cko0: 4.096 mhz output clock. cko1: 8.192 mhz output clock. cko2: 16.384 mhz output clock. cko3: 4.096 mhz, 8.192 mhz or 16.384 mhz programmable output clock. 32.768mhz if in multiplied clock mode. b10 155 fpi st-bus/gci-bus frame pulse input (5 v-tolerant schmitt-triggered input) this pin accepts the frame pulse which stays active for 61 ns, 122 ns or 244 ns at the frame boundary. the frame pulse frequency is 8 khz. the frame pulse associated with the cki must be applied to this pin. if the data rate is 16.384 mbps, a 61 ns wide frame pulse must be used. by default, the device accepts a negative frame pulse in st-bus format, but it can accept a positive frame pulse instead if the fpinp bit is set high in the control register (cr). it can accept a gci-formatted frame pulse by programming the fpinpos bit in the control register (cr) to high. b11 154 cki st-bus/gci-bus clock input (5 v-tolerant schmitt-triggered input) this pin accepts a 4.096 mhz, 8.192 mhz or 16.384 mhz clock. in divided clock mode the clock fr equency applied to this pin must be twice the highest input or output data rate. in multiplied clock mode the clock frequency applied to this pin must be twice the highest input data rate. the exception is, when data is running at 16.384 mbps, a 16.384 mhz clock must be used. by default, the clock falling edge defines the input frame boundary, but the device allows the clock rising edge to define the frame boundary by programming the ckinp bit in the control register (cr). pbga pin number lqfp pin number pin name description
ZL50023 data sheet 11 zarlink semiconductor inc. b6, c6, d5, d4, b4, b3, c5, c4, e3, c2, b2, d2, f3, f4, e2, f2, e1, d1, g1, f1, j1, h1, k1, l1, a7, a5, a6, a4, a3, a2, c1, b1 179, 180, 181, 182, 183, 184, 185, 187, 198, 200, 201, 202, 203, 204, 205, 206, 243, 244, 245, 246, 247, 248, 250, 252, 189, 190, 191, 192, 193, 194, 196, 197 sti0 - 31 serial input streams 0 to 31 (5 v- tolerant inputs with internal pull-downs) the data rate of each input stream can be selected independently using the stream input control registers (sicr[ n]). in the 2.048 mbps mode, these pins acce pt serial tdm data streams at 2.048 mbps with 32 channels per frame. in the 4.096 mbps mode, these pins accept serial tdm data streams at 4.096 mbps with 64 channels per frame. in the 8.192 mbps mode, these pins accept serial tdm data streams at 8.192 mbps with 128 channels per frame. in the 16.384 mbps mode, these pins accept tdm data streams at 16.384 mbps with 256 channels per frame. n4, p4, r4, p5, n13, p11, r14, r15, m15, l15, l13, l14, e14, d13, d15, c15, d16, e16, c16, b16, a13, a12, a10, a11, n1, m1, p1, r1, t2, t3, t5, t4 6, 7, 9, 10, 51, 52, 53, 54, 70, 72, 73, 74, 115, 116, 117, 118, 125, 126, 127, 128, 129, 130, 131, 132, 253, 254, 255, 256, 1, 2, 3, 4 stio0 - 31 serial output streams 0 to 31 (5 v-tolerant slew-rate-limited three-state i/os with enab led internal pull-downs) the data rate of each output stream can be selected independently using the stream output control registers (socr[n]). in the 2.048 mbps mode, these pins output serial tdm data streams at 2.048 mbps with 32 channels per frame. in the 4.096 mbps mode, these pins output serial tdm data streams at 4.096 mbps with 64 channels per frame. in the 8.192 mbps mode, these pins output serial tdm data streams at 8.192 mbps with 128 channels per frame. in the 16.3 84 mbps mode, these pins output serial tdm data streams at 16. 384 mbps with 256 channels per frame.these output streams can be used as bi-directionals by programming bdh (bit 7) and bdl (bit 6) of internal mode selection (ims) register. r3, p6, r5, n5, p12, n15, p13, p15, n16, m16, l16, k16, h16, j16, g16, f16 11, 12, 13, 14, 55, 56, 58, 59, 75, 76, 77, 78, 119, 120, 122, 124 stohz0 - 15 serial output streams high impedanc e control 0 to 15 (5 v-tolerant slew-rate-li mited three-state outputs) these pins are used to enable (or disable) external three-state buffers. when an output channel is in the high impedance state, the stohz drives high for the dur ation of the corresponding output channel. when the stio channel is active, the stohz drives low for the duration of the corres ponding output channel. stohz outputs are available for stio0 - 15 only. pbga pin number lqfp pin number pin name description
ZL50023 data sheet 12 zarlink semiconductor inc. b15 141 ode output drive enable (5 v-tolerant input with internal pull-up) this is the output enable control for stio0 - 31 and the output-driven-high control for stoh z0 - 15. when it is high, stio0 - 31 and stohz0 - 15 are enabled. when it is low, stio0 - 31 are tristated and stohz0 - 15 are driven high. m4, n6, r6, p7, r7, n7, m8, n8, p8, r8, m9, n9, r9, n10, p9, r10 16, 18, 20, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 36, 37, 38 d0 - 15 data bus 0 to 15 (5 v-tolerant slew-rate-limi ted three-state i/os) these pins form the 16-bit data bus of the microprocessor port. n12 44 dta _rdy data transfer acknowledgment_ready (5 v-tolerant three-state output) this active low output indicates that a data bus transfer is complete for the motorola interface. for the intel interface, it indicates a transfer is completed when this pin goes from low to high. an external pull-up resistor must hold this pin at high level for the motorola mode. an external pull-down resistor must hold this pin at low level for the intel mode. r11 40 cs chip select (5 v-tolerant input) active low input used by the motorola or intel microprocessor to enable the microprocessor port access. n11 39 r/w _wr read/write_write (5 v-tolerant input) this input controls the directio n of the data bus lines (d0 - 15) during a microprocessor access. fo r the motorola interface, this pin is set high and low for the read and write access respectively. for the intel interface, a write ac cess is indicated when this pin goes low. r12 42 ds _rd data strobe_read (5 v-tolerant input) this active low input works in conjunction with cs to enable the microprocessor port read and wr ite operations for the motorola interface. a read access is indicated when it goes low for the intel interface. k13, k15, k14, j11, j12, j13, j15, h11, j14, h12, h13, h15, g12, g13 82, 84, 86, 87, 88, 89, 90, 91, 92, 93, 94, 96, 98, 99 a0 - 13 address 0 to 13 (5 v-tolerant inputs) these pins form the 14-bit addres s bus to the internal memories and registers. pbga pin number lqfp pin number pin name description
ZL50023 data sheet 13 zarlink semiconductor inc. 3.0 device overview the device has thirty-two st-bus/gci-bus inputs (sti0 - 31) and thirty-two st-bus/gci-bus outputs (stio0 - 31). stio0 - 31 can also be configured as bi-directional pins, in which case sti0 - 31 will be ignored. it is a non-blocking digital switch with 4096 64 kbps channels and is capabl e of performing rate conversion between st-bus/gci-bus inputs and st-bus/gci-bus outputs. the st-bus/gci-bus inputs accept serial input data streams with data rates of 2.048 mbps, 4.096 mbps, 8.192 mbps and 16.384 mbps on a per-stream basis. the st-bus/gci-bus outputs deliver serial data streams with da ta rates of 2.048 mbps, 4.096 mbps and, 8.192 mbps and 16.384 mbps on a per-stream basis. the device also provides sixteen high impedance control outputs (stohz0 - 15) to support the use of external st-bus/gci-bus tr istate drivers for the first sixteen st-bus/gci-bus outputs (stio0 -15). by using zarlink?s message mode capability, microproc essor data stored in the connection memory can be broadcast to the output streams on a pe r-channel basis. this feature is usef ul for transferring control and status information for external circuits or other st-bus/gci-bus devices. the device uses the st-bus/gci-bus input frame pulse (f pi) and the st-bus/gci-bus input clock (cki) to define the input frame boundary and timing for sampling the st-bus/gci-bus input st reams with various data rates. the output data streams will be driven by and have their timing defined by fpi and cki in divided clock mode (clkm bit 11 table 13, control register ( cr) bits. in multiplied clock mode, t he output data streams will be driven by an internally generated clock, which is multiplied from cki in ternally. in multiplied clock mode, the output data streams will be driven by an internally generated cloc k, which is multiplied from cki internally. there are two clock modes for this device: the first is the divided clock mode. in this mode, output streams are clocked by in put cki. therefore the output streams have exactly the same jitter as the input streams. the output data ra te can be the same as or lower than the input data rate, but the output dat a rate cannot be higher than what ck i can drive. for example, if cki is 4.096 mhz, the output data rate canno t be higher than 2.048 mbps.the second clock mode is called multiplied clock mode. in this mode, cki is used to generate a 16. 384 mhz clock internally, and output streams are driven by this internal clock. in multiplied clock mode, the data rate of output streams can be any rate, but output jitter may not be exactly the same as input jitter. a motorola or intel compatible non-multiplexed microproce ssor port allows users to pr ogram the device to operate in various modes under different swit ching configurations. users can use the microprocessor port to perform internal register and memory read a nd write operations. the microprocessor port has a 16-bit data bus, a 14-bit address bus and six control signals (mot_intel , cs , ds _rd , r/w _wr and dta _rdy). m13 41 mot_intel motorola_intel (5 v-tolerant input with internal pull-up) this pin selects the motorola or intel microprocessor interface to be connected to the device. when this pin is unconnected or connected to high, motorola interfac e is assumed. when this pin is connected to ground, intel interface should be used. g2 211 reset device reset (5 v-tolerant input with internal pull-up) this input (active low) puts the device in its reset state that disables the stio0 - 31 drivers and drives the stohz0 - 15 outputs to high. it also preloads registers with default values and clears all internal counters. to en sure proper reset action, the reset pin must be low for longer than 1 s. upon releasing the reset signal to the device, the first mi croprocessor access cannot take place for at least 600 s due to the time requ ired to stabilize the device from the power-down state. refer to section 13.2 on page 30 for details. pbga pin number lqfp pin number pin name description
ZL50023 data sheet 14 zarlink semiconductor inc. the device supports the mandatory requirements of the ieee-1149.1 (j tag) standard via the test port. 4.0 data rates and timing the ZL50023 has 32 serial data inputs and 32 serial da ta outputs. each stream can be individually programmed to operate at 2.048 mbps, 4.096 mbps, 8.192 mbps or 16. 384 mbps. depending on the data rate there will be 32 channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 s frame. the output streams can be programmed to operate as bi-d irectional streams. the output streams are divided into two groups to be programmed into bi-directional mode. by setting bdl (bit 6) in the internal mode selection (ims) register, input streams 0 - 15 (sti0 - 15) are internally tied low, and output streams 0 - 15 (stio0 - 15) are set to operate in a bi-directional mode. similarly, when bdh (bit 7) in the internal mode sele ction (ims) register is set, input streams 16 - 31 (sti16 - 31) are internally tied lo w, and output streams 16 - 31 (s tio16 - 31) are set to operate in bi-directional mode. the groups do not have to be set into the same mode. therefore it is possible to have half of the streams operating in bi-directional mode while the ot her half is operating in normal input/output mode. the input data rate is set on a per-stream basis by progr amming stin[n]dr3 - 0 (bits 3 - 0) in the stream input control register 0 - 31 (sicr0 - 31). the output data ra te is set on a per-stream basis by programming sto[n]dr3 - 0 (bits 3 - 0) in the stream output control register 0 - 31 (socr0 - 31). the output data rates do not have to match or follow the input data rates.the maximum number of channels switched is limited to 4096 channels. if all 32 input streams were operating at 16.384 mbps (256 channels per stream), this would result in 8192 channels. memory limitations prevent the device from operating at this capacity. a maximum capacity of 4096 channels will occur if half of the total streams are operating at 16.384 mbps or all streams are operat ing at 8.192 mbps. with all streams operating at 4.09 mbps, the switching capacity is reduced to 2048 channels. and with all streams operating at 2.048 mbps, the capacity will be further reduc ed to 1024 channels. however, as each stream can be programmed to a different data rate, an y combination of data rates can be ac hieved, as long as the total channel count does not exceed 4096 channels. it should be noted that only full stream can be programmed for use. the device does not allow fractional streams. 4.1 external high im pedance control, stohz0 - 15 there are 16 external high impedance control signals, stohz0 - 15, that are used to cont rol the external drivers for per-channel high impedance operations. only the first sixteen st-bus/gci-bus (stio0 - 15) outputs are provided with corresponding stohz signals. the stohz outputs deliver the appropriate num ber of control timeslot channels based on the output stream data rate. each contro l timeslot lasts for one channel time. when the ode pin is high and the osb (bit 2) of the control register (cr) is also high, stohz0 - 15 are enabled. when the ode pin, osb (bit 2) of the control register (cr) or the reset pin is low, stohz0 - 15 are dr iven high, together with all the st-bus/gci-bus outputs being tristated. under normal operation, the correspondi ng stohz outputs of any unused st-bus/gci-bus channel (high impedance) are driven high. refer to figure 16 on page 25 for a diagrammatical explanation. 4.2 input clock (cki) and input frame pulse (fpi) timing the frequency of the input clock (cki) for the ZL50023 dep ends on the timing mode selected. in divided clock mode cki, must be at least twice the highes t input or output data rate. for exampl e, if the highest input data rate is 4.096 mbps and the highest output data rate is 8.192 mbps, the input clock, cki, must be 16.384 mhz, which is twice the highest overall data rate. the only exception to this is for 16.384 mbps input or output data. in this case, the input clock, cki, is equal to the data rate. the input fr ame pulse, fpi, must always fo llow cki. in multiplied clock mode the frequency of cki must be at least twice the highest input data rate regardless of the output data rate. an apll is used to multiple cki to generate an internal clock that is used to clock the output clocks and stio streams. following the example above, if the highe st input data rate is 4.096 mbps, th e input clock, cki, must be 8.192 mhz, regardless of the output data rate. the on ly exception to this is for 16.384 mbps input or output data. in this case, the input clock, cki, is equal to the data rate. the input frame pulse, fpi, must always follow cki. in either mode the user has to program the ckin1 - 0 (bits 6 - 5) in the control register (cr) to indicate the width of the input frame pulse and the frequency of the input clock supplied to the device.
ZL50023 data sheet 15 zarlink semiconductor inc. the ZL50023 accepts positive and negative st-bus/gci-bus input clock and input frame pulse formats via the programming of ckinp (bit 8) and fpinp (bit 7) in the control register (cr). by def ault, the device accepts the negative input clock format and st-bus format frame pulses . however, the switch can also accept a positive-going clock format by programming ckinp (bit 8) in the cont rol register (cr). a gci-bus format frame pulse can be used by programming fpinpos (bit 9) and fpin p (bit 7) in the co ntrol register (cr). highest input or output data rate ckin 1-0 bits input clock rate (cki) input frame pulse (fpi) 16.384 mbps or 8.192 mbps 00 16.384 mhz 8 khz (61 ns wide pulse) 4.096 mbps 01 8.192 mhz 8 khz (122 ns wide pulse) 2.048 mbps 10 4.096 mhz 8 khz (244 ns wide pulse) table 1 - cki and fpi configurations highest input or output data rate ckin 1-0 bits input clock rate (cki) input frame pulse (fpi) 8.192 mbps or 16.384 mbps 00 16.384 mhz 8 khz (61 ns wide pulse) 4.096 mbps 01 8.192 mhz 8 khz (122 ns wide pulse) 2.048 mbps 10 4.096 mhz 8 khz (244 ns wide pulse) table 2 - cki and fpi configurations for divided clock modes highest input data rate ckin 1-0 bits input clock rate (cki) input frame pulse (fpi) 8.192 mbps or 16.384 mbps 00 16.384 mhz 8 khz (61 ns wide pulse) 4.096 mbps 01 8.192 mhz 8 khz (122 ns wide pulse) 2.048 mbps 10 4.096 mhz 8 khz (244 ns wide pulse) table 3 - cki and fpi configurations for multiplied clock mode
ZL50023 data sheet 16 zarlink semiconductor inc. figure 4 - input timing when cki n1 - 0 bits = ?10? in the cr figure 5 - input timing when cki n1 - 0 bits = ?01? in the cr fpi (244 ns) fpinp = 0 fpinpos = 0 fpi (244 ns) fpinp = 1 fpinpos = 0 fpi (244 ns) fpinp = 0 fpinpos = 1 fpi (244 ns) fpinp = 1 fpinpos = 1 cki (4.096 mhz) ckinp = 0 cki (4.096 mhz) ckinp = 1 76 1 0 0 7 sti (2.048 mbps) channel 0 channel 31 st-bus gci-bus fpi (122 ns) fpinp = 0 fpinpos = 0 fpi (122 ns) fpinp = 1 fpinpos = 0 fpi (122 ns) fpinp = 0 fpinpos = 1 fpi (122 ns) fpinp = 1 fpinpos = 1 cki (8.192 mhz) ckinp = 0 cki (8.192 mhz) ckinp = 1 sti (4.096 mbps) channel 0 channel 63 6 54 1 0 2 76 7 1 0 st-bus gci-bus
ZL50023 data sheet 17 zarlink semiconductor inc. figure 6 - input timing when ckin1 - 0 = ?00? in the cr 5.0 st-bus and gci-bus timing the ZL50023 is capable of operating using either the st -bus or gci-bus standards. the output timing that the device generates is defined by the bus standard. in th e st-bus standard, the output frame boundary is defined by the falling edge of cko while fpo is low. in the gci-bu s standard, the frame boundary is defined by the rising edge of cko while fpo goes high. the data rates define the number of channels that are available in a 125 s frame pulse period. by default, the ZL50023 is configured for st-bus input and output timing. to se t the input timing to conform to the gci-bus standard, fpinpos (bit 9) and fpinp (bit 7) in the control register (cr) must be set. to set output timing to conform to the gci-bus standard, fpo[n]p and fpo[n]po s must be set in the output clock and frame pulse selection register (ocfsr). the cko[n]p bits in the ou tput clock and frame pulse selection register control the polarity (positive-going or negat ive-going) of the output clocks. 6.0 output timing generation the ZL50023 generates frame pulse and cl ock timing. there are four output fr ame pulse pins (fpo0 - 3) and four output clock pins (cko0 - 3). all output frame pulses are 8 khz output signals. by default, the output frame boundary is defined by the falling edge of the cko0, while fpo0 is low. at the out put frame boundary, the cko1, cko2 and cko3 output clocks will by default have a falling edge, while fp o1, fpo2 and fpo3 will be low. the duration of the frame pulse low cycle and the frequency of the corresponding output clock are shown in table 4 on page 17. every frame pulse and clock out put can be tristated by programming the enable bits in the internal mode selection (ims) register. pin name output timing rate output timing unit table 4 - output timing generation fpi (61 ns) fpinp = 0 fpinpos = 0 fpi (61 ns) fpinp = 1 fpinpos = 0 fpi (61 ns) fpinp = 0 fpinpos = 1 fpi (61 ns) fpinp = 1 fpinpos = 1 cki (16.384 mhz) ckinp = 0 cki (16.384 mhz) ckinp = 1 sti (8.192 mbps) channel 0 channel n = 127 6 5 4 3 2 1 3 2 1 0 5 4 7 6 5 7 1 0 sti (16.384 mbps) channel 0 channel n = 255 6 7 4 5 2 3 0 1 6 7 4 5 2 3 2 3 0 1 6 7 4 5 2 3 6 7 4 5 2 3 0 1 2 3 0 1 st-bus gci-bus
ZL50023 data sheet 18 zarlink semiconductor inc. the output timing is dependent on the timing mode that is selected. when the device is in divided clock mode, the frequencies on cko0 - 3 cannot be greater than the input clock, cki. for exam ple, if the input clock is 8.192 mhz, the cko2 pin will not produce a valid output clock and the cko3 pin can only be programmed to output a 4.096 mhz or 8.192 mhz clock signal. the device also delivers positive or negative output frame pulse and st-bus/gci-bus output clock formats via the programming of various bits in the output clock and frame pulse selecti on register (ocfsr). by default, the device delivers the negative output clock format. the zl 50023 can also deliver gci-bu s format output frame pulses by programming bits of the output clock and frame pulse selection register (ocfsr). as there is a separate bit setting for each frame pulse output, some of the output s can be set to operate in st-bus mode and others in gci-bus mode. the following figures describe the us age of the fpo0p, fpo1p, fpo2p, fpo3p, cko0p, cko1p, cko2p and cko3p bits to generate the fpo0 - 3 and cko0 - 3 timing. figure 7 - output timing for cko0 and fpo0 fpo0 pulse width 244 ns cko0 4.096 mhz fpo1 pulse width 122 ns cko1 8.192 mhz fpo2 pulse width 61 ns cko2 16.384 mhz fpo3 pulse width 244, 122, 61 or 30 ns cko3 4.096, 8.192, 16.384 or 32.768 mhz table 4 - output timing generation ckofpo0en = 1 fpo0p = 0 fpo0pos = 0 ckofpo0en = 1 fpo0p = 1 fpo0pos = 0 ckofpo0en = 1 fpo0p = 0 fpo0pos = 1 ckofpo0en = 1 fpo0p = 1 fpo0pos = 1 ckofpo0en = 1 cko0p = 0 cko0 = 4.096 mhz ckofpo0en = 1 cko0p = 1 cko0 = 4.096 mhz st-bus gci-bus
ZL50023 data sheet 19 zarlink semiconductor inc. figure 8 - output timing for cko1 and fpo1 figure 9 - output timing for cko2 and fpo2 ckofpo1en = 1 fpo1p = 0 fpo1pos = 0 ckofpo1en = 1 fpo1p = 1 fpo1pos = 0 ckofpo1en = 1 fpo1p = 0 fpo1pos = 1 ckofpo1en = 1 fpo1p = 1 fpo1pos = 1 ckofpo1en = 1 cko1p = 0 cko1 = 8.192 mhz ckofpo1en = 1 cko1p = 1 cko1 = 8.192 mhz st-bus gci-bus ckofpo2en = 1 fpo2p = 0 fpo2pos = 0 ckofpo2en = 1 fpo2p = 1 fpo2pos = 0 ckofpo2en = 1 fpo2p = 0 fpo2pos = 1 ckofpo2en = 1 fpo2p = 1 fpo2pos = 1 ckofpo2en = 1 cko2p = 0 cko2 = 16.384 mhz ckofpo2en = 1 cko2p = 1 cko2 = 16.384 mhz st-bus gci-bus
ZL50023 data sheet 20 zarlink semiconductor inc. figure 10 - output timing for cko3 and fpo3 with ck0fpo3sel1-0=?11? ckofpo3en = 1 ckofpo3sel1-0 = 11 fpo3p = 0 fpo3pos = 0 ckofpo3en = 1 ckofpo3sel1-0 = 11 fpo3p = 1 fpo3pos = 0 ckofpo3en = 1 ckofpo3sel1-0 = 11 fpo3p = 0 fpo3pos = 1 ckofpo3en = 1 ckofpo3sel1-0 = 11 fpo3p = 1 fpo3pos = 1 ckofpo3en = 1 ckofpo3sel1-0 = 11 cko3p = 0 cko3 = 32.768 mhz ckofpo3en = 1 ckofpo3sel1-0 = 11 cko3p = 1 cko3 = 32.768 mhz note: when ckofpo3sel1-0 = ?00,? the output for fpo3 and cko3 follow the same as figure 7: output timing for cko0 and fpo0 when ckofpo3sel1-0 = ?01,? the output for fpo3 and cko3 follow the same as figure 8: output timing for cko1 and fpo1 when ckofpo3sel1-0 = ?10,? the output for fpo3 and cko3 follow the same as figure 9: output timing for cko2 and fpo2 st-bus gci-bus
ZL50023 data sheet 21 zarlink semiconductor inc. 7.0 data input delay and data output advancement various registers are provi ded to adjust the input delay and output advancement for each input and output data stream. the input bit delay and output bit advancement ca n vary from 0 to 7 bits for each individual stream. if input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. the sampling point can vary from 1/4 to 4/4 with a 1/4-bit increment for all input streams, unless the stream is operating at 16.384 mbps, in which case the fractional bit delay has a 1/2-bit increment. by default, the sampling point is set to the 3/4-bit location for non-16.384 mbps data rates and the 1/2-bit location for the 16.384 mbps data rate. the fractional output bit advancement ca n vary from 0 to 3/4 bits, again wi th a 1/4-bit increment unless the output stream is operating at 16.384 mbps, in wh ich case the output bit advancement ha s a 1/2-bit increment from 0 to 1/2 bit. by default, there is 0 output bit advancement. although input delay or output advancem ent features are available on stream s which are operating in bi-directional mode it is not recommended, as it can easily cause bus co ntention. if users require this function, special attention must be given to the timing to en sure contention is minimized. 7.1 input bit delay programming the input bit delay programming feature provides us ers with the flexibility of hand ling different wire delays when designing with source str eams for different devices. by default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame boundary (assuming st-bus formatting). the input delay is enabled by stin[n]bd2-0 (bits 8 - 6) in the stream input control register 0 - 31 (sicr0 - 31) as descri bed in section 24 on page 46. the input bit delay can range from 0 to 7 bits. figure 11 - input bit delay timing diagram (st-bus) fpi sti[n] bit delay = 0 (default) channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 channel 2 2 1 0 4 3 last channel sti[n] bit delay = 1 channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 channel 2 2 1 0 4 3 last channel bit delay = 1 5 note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, and 8.192 and 16.384 mbps modes respectively.
ZL50023 data sheet 22 zarlink semiconductor inc. 7.2 input bit sampling point programming in addition to the input bit delay featur e, the ZL50023 allows users to change the sampling point of the input bit by programming stin[n]smp 1-0 (bits 5 - 4) in the stream input control register 0 - 31 (sicr0 - 31). for input streams operating at any rate except 16.384 mbps, the defaul t sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position. when the stream is operating at 16.384 mbps, the default sampling point is 1/2 bit and can be adjusted to a 4/4 bit position. figure 12 - input bit sampling point programming fpi sti[n] stin[n]smp1-0 = 01 (2, 4 or 8 mbps) channel 0 last channel sampling point = 1/4 bit sti[n] stin[n]smp1-0 = 10 (2, 4 or 8 mbps) stin[n]smp1-0 = 00 (16 mbps - default) channel 0 last channel sampling point = 1/2 bit sti[n] stin[n]smp1-0 = 00 (2, 4 or 8 mbps - default) channel 0 last channel sampling point = 3/4 bit 1 0 7 6 2 note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps mode respectively sti[n] stin[n]smp1-0 = 11 (2, 4 or 8 mbps) stin[n]smp1-0 = 10 (16 mbps) channel 0 last channel sampling point = 4/4 bit 5 1 0 7 6 5 1 0 7 6 5 1 0 7 6 2 5
ZL50023 data sheet 23 zarlink semiconductor inc. the input delay is controlled by stin[n]bd2-0 (bits 8 - 6) to control the bit shift and stin[n]smp1 - 0 (bits 5 - 4) to control the sampling point in the stream i nput control register 0 - 31 (sicr0 - 31). figure 13 - input bit delay and factional sampling point 7.3 output advancement programming this feature is used to advance the output data of indi vidual output streams with respect to the output frame boundary. each output stream has its own bit advancem ent value which can be programmed in the stream output control register 0 - 31 (socr0 - 31). by default, all output streams have ze ro bit advancement such that bit 7 is the first bit that appears after the output frame boundary (assuming st-bus format ting). the output advancement is enab led by sto[n]ad 2 - 0 (bits 6 - 4) of the stream output control register 0 - 31 (socr0 - 31) as described in section 26 on page 49. the output bit advancement can vary from 0 to 7 bits. nominal channel n+1 boundary 7 6 5 4 3 2 1 0 7 0 000 01 000 10 000 00 (default) 000 11 001 01 001 10 001 00 001 11 010 01 010 10 010 00 010 11 011 01 011 10 011 00 011 11 111 00 111 10 111 01 110 11 110 00 110 10 110 01 101 11 101 00 101 10 101 01 100 11 100 00 100 10 100 01 111 11 the first 3 bits represent stin[n]bd2 - 0 for setting the bit delay the second set of 2 bits represent stin[n]smp1 - 0 for setting the sampling point offset sti[n] nominal channel n boundary example: with a setting of 011 10 the offs et will be 3 bits at a 1/2 sampling point note: italic settings can be used in 16 mbps mode (1/2 and 4/4 sampling point)
ZL50023 data sheet 24 zarlink semiconductor inc. figure 14 - output bit advancement timing diagram (st-bus) 7.4 fractional output bit advancement programming in addition to the output bit advanceme nt, the device has a fractional output bit advancement feature that offers better resolution. the fractional output bit advancement is useful in compensating for varying parasitic load on the serial data output pins. by default all of the streams have zero fr actional bit advancement such that bit 7 is the first bit that appears after the output frame boundary. the fractional output bit advancement is enabled by sto[n]fa 1 - 0 (bits 8 - 7) in the stream output control register 0 - 31 (socr0 - 31). for all streams running at any data rate except 16.384 mbps the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits. fo r streams operating at 16.384 mbps, the fractional bit advancement can be set to either 0 or 1/2 bit. figure 15 - output fractional bit advancement timing diagram (st-bus) fpi stio[n] bit adv = 0 (default) channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 channel 2 2 1 0 4 3 last channel stio[n] bit adv = 1 channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 channel 2 2 1 0 3 last channel bit advancement = 1 note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps modes respectively. 2 1 fpi stio[n] sto[n]fa1-0 = 00 (default 2, 4, 8 or 16mbps) channel 0 7 last channel stio[n] sto[n]fa1-0 = 01 (2, 4 or 8 mbps) channel 0 last channel fractional bit advancement = 1/4 bit 6 5 2 1 0 stio[n] sto[n]fa1-0 = 10 (2, 4 or 8mbps) sto[n]fa1-0 = 01 (16 mbps) channel 0 last channel fractional bit advancement = 1/2 bit stio[n] sto[n]fa1-0 = 11 (2, 4 or 8 mbps) channel 0 last channel fractional bit advancement = 3/4 bit note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps modes respectively. 7 6 5 1 0 7 6 5 1 0 7 6 5 1 0 4 4 4
ZL50023 data sheet 25 zarlink semiconductor inc. 7.5 external high impedance control advancement the external high impedance signals can be programmed to better match the timing required by the external buffers. by default, the output timing of the stohz sig nals follows the programmed channel delay and bit offset of their corresponding st-bus/gci-bus output streams. in addition, for all high impedan ce streams operating at any data rate except 16.384 mbps, the user can advance the stoh z signals a further 0, 1/4, 1/2, 3/4 or 4/4 bits by programming stohz[n]a 2 - 0 (bit 11 - 9) in the stream ou tput control register. when the stream is operating at 16.384 mbps, the additional stohz advancement can be se t to 0, 1/2 or 4/4 bits by programming the same register. figure 16 - channel switching external high impedance control timing 8.0 data delay through the switching paths the switching of information from the i nput serial streams to the output serial streams results in a throughput delay. the device can be programmed to per form timeslot interchange functions with different throughput delay capabilities on a per-channel basis. for voice applicati ons, select variable throughput delay to ensure minimum delay between input and output data. in wideband data applic ations, select constant delay to maintain the frame integrity of the information through the switch. the de lay through the device varies according to the type of throughput delay selected by the v/c (bit 14) in the connection memory low when cmm = 0. 8.1 variable delay mode variable delay mode causes the output channel to be transmitted as soon as possible. this is a useful mode for voice applications where the minimum throughput delay is more important than frame integrity. the delay through the switch can vary from 7 channels to 1 frame + 7 channel s. to set the device into variable delay mode, varen (bit 4) in the control regist er (cr) must be set before v/c (bit 14) in the connection memory low when cmm = 0. if the varen bit is not set and the device is programme d for variable delay mode, t he information read on the output stream will not be valid. ch0 ch1 ch2 ch3 last-2 last-1 last ch0 last hiz fpi stio[n] stohz[n] stohz[n] (with advancement) (default = no advancement) stohz advancement (programmable in 4 steps of 1/4 bit for 2.048 mbps, 4.096 mbps and 8.192 mbps programmable in 2 steps of 1/2 bit for 16.384 mbps) note: n = 0 to 15 note: last = last channel of 31, 63, 127 and 255 for 2.048 mbps, 4.096 mbps, 8.192 mbps and 16.384 mbps modes respectively. output frame boundary
ZL50023 data sheet 26 zarlink semiconductor inc. in variable delay mode, the delay depends on the combination of the source and destination channels of the input and output streams. for example, if stream 4 channel 2 is switched to stream 5 channel 9 with variable dela y, the data will be output in the same 125 s frame. contrarily, if stream 6 channel 1 is sw itched to stream 9 channel 3, the information will appear in the following frame. figure 17 - data throughput delay for variable delay 8.2 constant delay mode in this mode, frame integrity is maintained in all switchin g configurations. the delay though the switch is 2 frames - input channel + output channel. this can re sult in a minimum of 1 frame + 1 chan nel delay if the last channel on a stream is switched to the first channel of a stream. the maximum delay is 3 frames - 1 channel. this occurs when the first channel of a stream is switched to the last channel of a stream. the cons tant delay mode is available for all output channels. the data throughput delay is expressed as a function of st-bus/gci-bus frames, input channel number (m) and output channel number (n). the data throughput delay (t) is: t = 2 frames + (n - m) m = input channel number n = output channel number n-m <= 0 0 < n-m < 7 n-m = 7 n-m > 7 stio < sti stio >= sti t = delay between input and output 1 frame - (m-n) 1 frame + (n-m) n-m table 5 - delay for variable delay mode l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch4 ch5 ch6 ch4 ch5 ch6 ch4 ch5 ch6 ch7 ch8 ch9 ch7 ch8 ch9 ch7 ch8 ch9 ch7 ch8 ch9 sti4 ch2 stio5 ch9 sti6 ch1 stio9 ch3 frame n frame n + 1 l = last channel = 31, 63, 127, or 255 for 2.048 mbps, 4.096 mbps, 8.192 mbps, or 16.384 mbps respectively
ZL50023 data sheet 27 zarlink semiconductor inc. the constant delay mode is controlled by v/c (bit 14) in the connection memory low when cmm = 0. when this bit is set low, the channel is in constant delay mode. if vare n (bit 4) in the control register (cr) is set (to enable variable throughput dela y on a chip-wide basis), the de vice can still be programmed to operate in c onstant delay mode. figure 18 - data throughput delay for constant delay 9.0 connection memory description the connection memory consists of two blocks, connection memory low (cm_l) and connection memory high (cm_h). the cm_l is 16 bits wide and is used for channel switching and other special modes. the cm_h is 5 bits wide and is used for the voice coding function. when uaen (bit 15) of the connection memory low (cm_l) is low, -law/a-law conversion will be turn ed off and the contents of cm_h w ill be ignored. each connection memory location of the cm_l or cm_h can be read or written vi a the 16 bit microprocessor port within one microprocessor access cycle. see table 31 on page 52 for the address mapp ing of the connection memory. any unused bits will be reset to zero on the 16-bit data bus. for the normal channel switching operat ion, cmm (bit 0) of the connection memory low (cm_l) is programmed low. sca7 - 0 (bits 8 - 1) indicate the source (input) chann el address and ssa4 - 0 (bits 13 - 9) indicate the source (input) stream address. the 5-bit contents of the cm_h will be ignored during the normal channel switching mode without the -law/a-law conversion when uaen (bit 15) of t he connection memory low (cm_l) is set to zero. if -law/a-law conversion is required, t he cm_h bits must be programmed first to provide the voice/data information, the input coding law and the output coding law before t he assertion of uaen (bit 15) in the connection memory low. when cmm (bit 0) of the connection memory low (cm_l) is programmed high, the ZL50023 will operate in one of the special modes described in table 33 on page 54. w hen the per-channel message mode is enabled, msg7 - 0 (bit 10 - 3) in the connection memory low (cm_l) will be output via the serial data stream as message output data. when the per-channel message mode is enabled, the -law/a-law conversion can also be enabled as required. l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 sti stio sti stio l = last channel = 31, 63, 127, or 255 for 2.048 mbps, 4.096 mbps, 8.192 mbps, or 16.384 mbps respectively frame n frame n + 1 frame n + 2
ZL50023 data sheet 28 zarlink semiconductor inc. 10.0 connection memory block programming this feature allows for fast initialization of the conne ction memory after power up. 10.1 memory bloc k programming procedure 1. set mbpe (bit 3) in the control register (cr) from low to high. 2. configure bpd2 - 0 (bits 3 - 1) in the internal mode sele ction (ims) register to the desired values to be loaded into cm_l. 3. start the block progra mming by setting mbps (bit 0) in the internal mode selection register (ims) high. the val- ues stored in bpd2 - 0 will be loaded into bits 2 - 0 of all cm_l positions. the remaining cm_l locations (bits 15 - 3) and the programmable values in the cm_h (b its 4 - 0) will be load ed with zero values. the following tables show the resulting values that ar e in the cm_l and cm_h connection memory locations. note: bits 15 to 5 are reserved in connection memory high and should always be 0. it takes at least tw o frame periods (250 s) to complete a block program cycle. mbps (bit 0) in the control register (cr) will automatically reset to a low position after the block programming process has completed. mbpe (bit 3) in the internal mode sele ction (ims) register must be cleared from high to lo w to terminate the block programming process. this is not an automatic acti on taken by the device and must be performed manually. note : once the block program has been initiated, it can be terminated at any time prio r to completion by setting mbps (bit 0) in the control register (cr) or mbpe (bit 3) in the internal mode selection (ims) register to low. if the mbpe bit was used to terminate the block programming, the mbps bit will have to be set low before enabling other device operations. 11.0 device performance divided clock and multiplied clock modes this device has two main operating modes - di vided clock mode and multiplied clock mode. in multiplied clock mode, output clocks and frame pulses are generated based on cki and fpi. in divided clock mode, output clocks and frame pulses are directly divi ded from cki/fpi; therefore, the output clock rate cannot exceed the cki rate. in multiplied clock mode, the output clocks and frame pulses are generated from a clock internal to the device and are synchronized to cki and fp i. all specified frequencies are available on cko[0:3] in multiplied clock mode. bit1514131211109876543 2 1 0 value0000000000000bpd2bpd1bpd0 table 6 - connection memory low after block programming bit1514131211109876543 2 1 0 value0000000000000 0 0 0 table 7 - connection memory high after block programming
ZL50023 data sheet 29 zarlink semiconductor inc. 11.1 divided clock mode performance when the device is in divided clock mode, stio0 - 31 ar e driven by cki. in this mode, the output streams and clocks have the same amount of jitter as the input clock (cki), but the output data rate cannot exceed the input data rate defined by cki. for example, if cki is 4.096 mhz, the output data rate cannot be higher than 2.048 mbps, and the generated output clock rates cannot exceed 4.096 mhz. 11.2 multiplied clock mode performance when the device is in multiplied clock mode, device hardware is used to multiply cki internally. stio0 - are driven by this internally generated clock. in this mode, the output data rate can be any specified data rate, but the output streams and clocks may have different jitter characteristics from the input clock (cki). 12.0 microprocessor port the device provides access to the internal regi sters, connection memories and data memories via the microprocessor port. the microprocessor port is capable of supporting both motorola and intel non-multiplexed microprocessors. the micropro cessor port consists of a 16-bit parallel data bus (d15 - 0), 14-bit address bus (a13 - 0) and six control signals (mot_intel , cs , ds _rd , r/w _wr and dta _rdy). the data memory can only be read from the microprocessor port. for a data memory read operation, d7 - 0 will be used and d15 - 8 will output zeros. for a cm_l read or write oper ation, all bits (d15 - 0) of the data bus will be used. fo r a cm_h write operation, d4 - 0 of the data bus must be configured and d15 - 5 are ignored. d15 - 5 must be driven either high or low. for a cm_h read operation, d4 - 0 will be used and d15 - 5 will output zeros. refer to figure 20 on page 58, figure 21 on page 59, figure 22 on page 60 and figure 23 on page 61 for the microprocessor timing. 13.0 device reset and initialization the reset pin is used to reset the ZL50023. when this pin is low, the following functions are performed: ? synchronously puts the microprocessor port in a reset state ? tristates the stio0 - 31 outputs ? drives the stohz0 - 15 outputs to high ? preloads all internal registers with their default values (refer to the individual registers for default values) ? clears all internal counters cko0 4.096 mhz cko1 8.192 mhz cko2 16.384 mhz cko3 4.096 mhz, 8.192 mhz, 16.384 mhz or 32.768 mhz fpo0 8 khz (244 ns wide pulse) fpo1 8 khz (122 ns wide pulse) fpo2 8 khz (61 ns wide pulse) fpo3 8 khz (244 ns, 122 ns, 61 ns or 30 ns wide pulse) table 8 - generated output frequencies
ZL50023 data sheet 30 zarlink semiconductor inc. 13.1 power-up sequence the recommended power-up sequence is for the v dd_io supply (normally +3.3 v) to be established before the power-up of the v dd_core supply (normally +1.8 v). the v dd_core supply may be powered up at the same time as v dd_io , but should not ?lead? the v dd_io supply by more than 0.3 v. 13.2 device initialization on reset upon power up, the ZL50023 should be initialized as follows: ? set the ode pin to low to disable the stio0 - 31 outputs and to drive stohz0 - 15 to high ? set the trst pin to low to disable the jtag tap controller ? reset the device by pulsing the reset pin to zero for longer than 1 s ? after releasing the reset pin from low to high, wait for a certain period of time (see note below) for the device to stabilize from the power down state before the first microprocessor port access can occur ? program ckin1 - 0 (bit 6 -5) in the control register (cr) to define the frequency of the cki and fpi inputs ? wait at least 500 s prior to the next microport access (see note below) ? use the block programming mode to initialize the connection memory ? release the ode pin from low to high after the connection memory is programmed note : if cki is 16.384 mhz, the waiting time is 500 s; if cki is 8.192 mhz, the waiting time is 1 ms; if cki is 4.096 mhz, the waiting time is 2 ms. 13.3 software reset in addition to the hardware reset from the reset pin, the device can also be reset by using software reset srstsw (bit 1) in the software reset register (srr). 14.0 pseudorandom bit generation and error detection the ZL50023 has one bit error rate (ber) transmitter and one ber receiver for each pair of input and output streams, resulting in 32 transmitters connected to the output streams and 32 receiv ers associated with the input streams. each transmitter can generat e a ber sequence with a pattern of 2 15 -1 pseudorandom code (itu o.151). each transmitter can start at any loca tion on the stream and will last for a minimum of 1 channel to a maximum of 1 frame time (125 s). the ber receivers and transmitters are enabled by programming the rberen (bit 5) and tberen (bit 4) in the ims register. in order to save power, the 32 transmitters and/or receivers can be disabled. (this is the default state.) multiple connection memory locations can be programme d for ber tests such that the ber patterns can be transmitted for multiple consecutive output channels. if consecutive input channel s are not selected, the ber receiver will not compar e the bit patterns corr ectly. the number of ou tput channels which t he ber pattern occupies has to be the same as the number of channels defined in the ber length register (brlr) which defines how many ber channels are to be monitored by the ber receiver. for each input stream, there is a set of register s for the ber test. the registers are as follows: ? ber receiver control register ( brcr ) - st[n]cber (bit 1) is used to clear the bit receiver error register (brer). st[n]sber (bit 0) is used to enable the per-stream ber receiver. ? ber receiver start register ( brsr ) - st[n]brs7 - 0 (bit 7 - 0) defines the input channel from which the ber sequence will start to be compared. ? ber receiver length register ( brlr ) - st[n]bl8 - 0 (bit 8 - 0) define how many channels the sequence will last. depending on the data rate being used, the ber test can last for a maximum of 32, 64, 128 or 256 channels at the data rates of 2.048, 4.096, 8.192 or 16.384 mbps, respectively. the minimum length of the
ZL50023 data sheet 31 zarlink semiconductor inc. ber test is a single channel. the user must take care to program the correct channel length for the ber test so that the channel length does not exceed the to tal number of channels available in the stream. ? ber receiver error register ( brer ) - this read-only register contains the number of counted errors. when the error count reaches 0xffff, the ber counter will st op updating so that it will not overflow. st[n]cber (bit 1) in the ber receiver control register is used to reset the brer register. for normal ber operation, cmm (bit 0) must be 1 in the connection memory low (cm_l). pcc1 - 0 (bits 2 - 1) in the connection memory low must be programmed to ?10? to enable the per-stream based ber transmitters. for each stream, the length (or total number of channels) of ber testing can be as long as one whole frame, but the channels must be consecutive. upon completion of pr ogramming the connection memory, the corresponding ber receiver can be started by setting st[n ]sber (bit 0) in the brcr to high. there must be at least 2 frames (250 s) between completion of connection memory programming and starting the ber receiver before the ber receiver can correctly identify ber errors. a 16-bit ber counter is used to count the number of bit errors. 15.0 pcm a-law/ -law translation the ZL50023 provides per-channel code translation to be used to adapt pulse code modulation (pcm) voice or data traffic between networks which us e different encoding laws. code translation is valid in both connection mode and message mode. in order to use this feature, t he connection memory high (cm_h) ent ry for the output channel must be programmed. v /d (bit 4) defines if the traffic in the channel is voice or data. setting icl1 - 0 (bits 3 - 2) programs the input coding law and ocl1 - 0 (bits 1- 0) programs the output coding law as shown in table 9. the different code options are: for voice coding options, the it u-t g.711 a-law and itu-t g.711 -law are the standard rules for encoding. a-law without alternate bit inversion (abi) is an alternative code that does not invert the even bits (6, 4, 2, 0). -law without magnitude inversion (mi) is an al ternative code that does not perform in version of magnitude bits (6, 5, 4, 3, 2, 1, 0). when transferring data code, the option ?no code? does not in vert the bits. the alternat e bit inversion (abi) option inverts the even bits (6, 4, 2, 0) while the inverted alternat e bit inversion (abi) inverts the odd bits (7, 5, 3, 1). when the ?all bits inverted? option is selected, all of the bits (7, 6, 5, 4, 3, 2, 1, 0) are inverted. the input channel and output channel encoding law are configured independent ly. if the output channel coding is set to be different from the input chann el, the ZL50023 performs translation between the two standards. if the input and output encoding laws are set to the same standard, no translation occurs. as the v /d (bit 4) of the connection memory high (cm_h) must be set on a per-channel basis, it is not possible to translate between voice and data encoding laws. input coding (icl1- 0) output coding (ocl1 - 0) voice coding (v /d bit = 0) data coding (v /d bit = 1) 00 00 itu-t g.711 a-law no code 01 01 itu-t g.711 -law alternate bit inversion (abi) 10 10 a-law without alternate bit inversion (abi) inverted alternate bit inversion (abi) 11 11 -law without magnitude inversion (mi) all bits inverted table 9 - input and output voice and data coding
ZL50023 data sheet 32 zarlink semiconductor inc. 16.0 quadrant frame programming by programming the stream input quadr ant frame registers (siqfr0 - 31), users can divide one frame of input data into four quadrant frames and can force the lsb or msb of every input channel in these quadrants to one or zero for robbed-bit signaling. the four quadrant frames are defined as follows: when the quadrant frame control bits, stin[n]q3c2 - 0 (bit 11 - 9), stin[n]q2c2 - 0 (bit 8 - 6), stin[n]q1c2 - 0 (bit 5 - 3) or stin[n]q1c2 - 0 (bit 2 - 0), are set, the lsb or msb of every input channel in t he quadrant is forced to ?1? or ?0? as shown by the following table: note that quadrant frame programming and ber recept ion cannot be used simultaneously on the same input stream. 17.0 jtag port the jtag test port is implemented to meet the mandat ory requirements of the ieee -1149.1 (jtag) standard. the operation of the boundary-scan circuitry is controlled by an external test access port (tap) controller. 17.1 test access port (tap) the test access port (tap) accesses the ZL50023 test func tions. it consists of three input pins and one output pin as follows: ? test clock input (tck) - tck provides the clock for the test logic. tck does not interfere with any on-chip clock and thus remains independent in the functional mode. tck permits shifting of test data into or out of the boundary-scan register cells concurrently with t he operation of the device and without interfering with the on-chip logic. ? test mode selection inputs (tms) - the tap controller uses the logic signals received at the tms input to control test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to high when it is not driven from an external source. data rate quadrant 0 quadrant 1 quadrant 2 quadrant 3 2.048 mbps channel 0 - 7 channel 8 - 15 channel 16 - 23 channel 24 - 31 4.096 mbps channel 0 - 15 channel 16 - 31 channel 32 - 47 channel 48 - 63 8.192 mbps channel 0 - 31 channel 32 - 63 channel 64 - 95 channel 96 - 127 16.384 mbps channel 0 - 63 channel 64 - 127 channel 128 - 191 channel 192 - 255 table 10 - definition of the four quadrant frames stin[n]q[x]c[2:0] action 0xx normal operation 100 replaces lsb of every channel in quadrant x with ?0? 101 replaces lsb of every channel in quadrant x with ?1? 110 replaces msb of every channel in quadrant x with ?0? 111 replaces msb of every channel in quadrant x with ?1? note: x = 0, 1, 2, 3 table 11 - quadrant frame bit replacement
ZL50023 data sheet 33 zarlink semiconductor inc. ? test data input (tdi) - serial input data applied to this port is fed ei ther into the instruction register or into a test data register, depending on the sequence previous ly applied to the tms input. the registers are described in a subsequent section. the received input data is sampled at the rising edge of the tck pulse. this pin is internally pulled to high when it is not driven from an external source. ? test data output (tdo) - depending on the sequence previously applied to the tms input, the contents of either the instruction register or test data register are serially shif ted out towards tdo. the data from tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. ? test reset (trst ) - resets the jtag scan structure. this pin is internally pulled to high when it is not driven from an external source. 17.2 instruction register the ZL50023 uses the public instructions defined in the ieee-1149.1 standard. the jtag interface contains a four-bit instruction register. instructi ons are serially loaded into the instruct ion register from the tdi when the tap controller is in its shifted-or state. these instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the in struction is current and to define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. 17.3 test data registers as specified in the ieee-1149.1 standard, the ZL50023 jtag inte rface contains three test data registers: ? the boundary-scan register - the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the z l50023 core logic. ? the bypass register - the bypass register is a single stage shift register that provides a one-bit path from tdi to tdo. ? the device identification register - the jtag device id for the ZL50023 is 0c36714b h 17.4 bsdl a boundary scan description language (bsdl) file is availabl e from zarlink semiconductor to aid in the use of the ieee-1149.1 test interface. version <31:28> 0000 part number <27:12> 1100 0011 0110 0111 manufacturer id <11:1> 0001 0100 101 lsb <0> 1
ZL50023 data sheet 34 zarlink semiconductor inc. 18.0 register address mapping address a13 - a0 cpu access register name abbreviation reset by 0000 h r/w control register cr switch/hardware 0001 h r/w internal mode selection register ims switch/hardware 0002 h r/w software reset register srr hardware only 0003 h r/w output clock and frame pulse control register ocfcr hardware 0004 h r/w output clock and frame pulse selection register ocfsr hardware 0005 h r/w fpo_off0 register fpoff0 hardware 0006 h r/w fpo_off1 register fpoff1 hardware 0007 h r/w fpo_off2 register fpoff2 hardware 0010 h r/w internal flag regist er ifr switch/hardware 0011 h r only ber error flag register 0 berfr0 switch/hardware 0012 h r only ber error flag register 1 berfr1 switch/hardware 0013 h r only ber error flag register 2 berfr2 switch/hardware 0014 h r only ber error flag register 3 berfr3 switch/hardware 0100 h - 011f h r/w stream input control registers 0 - 31 sicr0 - 31 switch/hardware 0120 h - 013f h r/w stream input quadrant fr ame registers 0 - 31 siqfr0 - 31 switch/hardware 0200 h - 021f h r/w stream output control register s 0 - 31 socr0 - 31 switch/hardware 0300 h - 031f h r/w ber receiver start registers 0 - 31 brsr0 - 31 switch/hardware 0320 h - 033f h r/w ber receiver length registers 0 - 31 brlr0 - 31 switch/hardware 0340 h - 035f h r/w ber receiver control register s 0 - 31 brcr0 - 31 switch/hardware 0360 h - 037f h r only ber receiver error registers 0 - 31 brer0 - 31 switch/hardware table 12 - address map for registers (a13 = 0)
ZL50023 data sheet 35 zarlink semiconductor inc. 19.0 detailed register description bit name description 15 - 12 unused reserved. in normal functional mode, these bits must be set to zero. 11 clkm clock mode when this bit is set low the timing mode is set to divided clock mode when this bit is set high the timing mode is set to multiplied clock mode 10 unused reserved. in normal functional mode, these bits must be set to zero. 9fpinpos input frame pulse (fpi) position when this bit is low, fpi straddles frame boundary (as defined by st-bus). when this bit is high, fpi starts from frame boundary (as defined by gci-bus) 8ckinp clock input (cki) polarity when this bit is low, the cki falling edge aligns with the frame boundary. when this bit is high, the cki risi ng edge aligns with the frame boundary. 7fpinp frame pulse input (fpi) polarity when this bit is low, the input frame puls e fpi has the negative frame pulse format. when this bit is high, the input frame pulse fpi has the positive frame pulse format. 6 - 5 ckin1 - 0 input clock (cki) and fram e pulse (fpi) selection 4 varen variable delay mode enable when this bit is low, the variable delay mode is disabled on a device-wide basis. when this bit is high, the variable delay mode is enabled on a device-wide basis. 3 mbpe memory block programming enable when this bit is high, the connection me mory block programming mode is enabled to program the connection memory. when it is low, the memory block programming mode is disabled. table 13 - control register (cr) bits external read/write address: 0000 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000clk m 0fpin pos ckinp fpinp ckin 1 ckin 0 var en mbpe osb ms1 ms0 ckin1 - 0 fpi active period cki 00 61 ns 16.384 mhz 01 122 ns 8.192 mhz 10 244 ns 4.096 mhz 11 reserved
ZL50023 data sheet 36 zarlink semiconductor inc. 2osb output stand by bit: this bit enables the stio0 - 31 and the stohz0 -15 serial outputs. the following table describes the hiz control of the serial data outputs: note: unused output streams are tristated (stio = hiz, stohz = driven high). refer to socr0 - 31 (bit2 - 0). 1 - 0 ms1 - 0 memory select bits these two bits are used to select connection memory low, connection high or data mem- ory for access by cpu: bit name description table 13 - control register (cr) bits (continued) external read/write address: 0000 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000clk m 0fpin pos ckinp fpinp ckin 1 ckin 0 var en mbpe osb ms1 ms0 reset pin srstsw (in srr) ode pin osb bit stio0 - 31 stohz0 - 15 0 x x x hiz driven high 1 1 x x hiz driven high 1 0 0 x hiz driven high 1 0 1 0 hiz driven high 1011 active (controlled by cm) active (controlled by cm) ms1 - 0 memory selection 00 connection memory low read/write 01 connection memory high read/write 10 data memory read 11 reserved
ZL50023 data sheet 37 zarlink semiconductor inc. bit name description 15 - 9 unused reserved. in normal functional mode, these bits must be set to zero. 8stio_pd_ en stio pull-down enable when this bit is low, the pull-down re sistors on all stio pads will be disabled. when this bit is high, t he pull-down resistors on all stio pads will be enabled. 7bdh bi-directional contro l for streams 16-31 6bdl bi-directional contro l for streams 0-15 5 rberen prbs receiver enable when this bit is low, all the ber receiver s are disabled. to enable any ber receivers, this bit must be high. 4 tberen prbs transmitter enable when this bit is low, all the ber transmitters are disabled. to enable any ber transmitters, this bit must be high. 3 - 1 bpd2 - 0 block programming data these bits refer to the value to be loaded into the connection memory, whenever the memory block programming feature is acti vated. after the mbpe bit in the control register is set to high and the mbps bit in th is register is set to high, the contents of the bits bpd2 - 0 are loaded into bits 2 - 0 of the connection memory low. bits 15 - 3 of the connection memory low and bits 15 - 0 of connection memory high are zeroed. table 14 - internal mode selection register (ims) bits external read/write address: 0001 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000stio_ pd_en bdh bdl rber en tber en bpd 2 bpd 1 bpd 0 mbps bdh stio16 - 31 operation 0 normal operation: sti16-31 are inputs stio16-31 are outputs 1 bi-directional operation: sti16-31 tied low internally stio16-31 are bi-directional bdl stio0 - 15 operation 0 normal operation: sti0-15 are inputs stio0-15 are outputs 1 bi-directional operation: sti0-15 tied low internally stio0-15 are bi-directional
ZL50023 data sheet 38 zarlink semiconductor inc. 0 mbps memory block programming start: a zero to one transition of this bit starts the memory block progr amming function. the mbps and bpd2 - 0 bits in this register must be defined in the same write operation. once the mbpe bit in the control register is set to high, the device requires two frames to complete the block programmin g. after the programmi ng function has fin- ished, the mbps bit returns to low, indicating the operation is completed. when mbps is high, mbps or mbpe can be set to low to abort the pr ogramming operation. whenever the microprocessor writes a one to the mbps bit, the block programming function is started. as long as this bit is hi gh, the user must maintain the same logical value to the other bits in this register to avoid any change in the device setting. bit name description 15 - 2 unused reserved in normal functional mode, these bits must be set to zero. 1srstsw software reset bit for switch when this bit is low, switching blocks are in normal operation. when this bit is high, switching blocks are in software reset state. refer to table 12, ?address map for registers (a13 = 0)? on page 32 for details regarding which registers are affected. 0unused reserved in normal functional mode, these bits must be set to zero. table 15 - software reset register (srr) bits bit name description table 14 - internal mode selection register (ims) bits (continued) external read/write address: 0001 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000stio_ pd_en bdh bdl rber en tber en bpd 2 bpd 1 bpd 0 mbps external read/write address: 0002 h reset value: 0000 h 15141312111098765432 1 0 00000000000000srst sw 0
ZL50023 data sheet 39 zarlink semiconductor inc. bit name description 15 - 9 unused reserved in normal functional mode, these bits must be set to zero. 8 fpof2en fpo_off2 enable when this bit is high, output frame pulse fpo_off2 when this bit is low, output frame pulse fpo_off2. 7 fpof1en fpo_off1 enable when this bit is high, output frame pulse fpo_off1 is enabled. when this bit is low, output frame pulse fpo_off1 is in high impedance state. 6 fpof0en fpo_off0 enable when this bit is high, output frame pulse fpo_off0 is enabled. when this bit is low, output frame pulse fpo_off0 is in high impedance state. 5unused reserved in normal functional mode, these bits must be set to zero. 4unused reserved in normal functional mode, these bits must be set to zero. 3ckofpo3 en cko3 and fpo3 enable when this bit is high, output clock cko3 and output frame pulse fpo3 are enabled. when this bit is low, cko3 and fpo3 are in high impedance state. 2ckofpo2 en cko2 and fpo2 enable when this bit is high, output clock cko2 and output frame pulse fpo2 are enabled. when this bit is low, cko2 and fpo2 are in high impedance state. 1ckofpo1 en cko1 and fpo1 enable when this bit is high, output clock cko1 and output frame pulse fpo1 are enabled. when this bit is low, cko1 and fpo1 are in high impedance state. 0ckofpo0 en cko0 and fpo0 enable when this bit is high, output clock cko0 and output frame pulse fpo0 are enabled. when this bit is low, cko0 and fpo0 are in high impedance state. table 16 - output clock and frame pulse control register (ocfcr) bits external read/write address: 0003 h reset value: 0000 h 1514131211109 8 7 6 5 4 3210 0000000fpof2 en fpof1 en fpof0 en 00cko fpo3 en cko fpo2 en cko fpo1 en cko fpo0 en
ZL50023 data sheet 40 zarlink semiconductor inc. bit name description 15 - 14 unused reserved in normal functional mode, these bits must be set to zero. 13 - 12 ckofpo3 sel1 - 0 output clock (cko3) frequency and ou tput frame pulse (fpo3) pulse cycle selection 11 cko3p output clock (cko3) polarity selection when this bit is low, the output clock cko3 falling edge aligns with the frame boundary. when this bit is high, the output clock cko3 rising edge aligns with the frame boundary. 10 fpo3p output frame pulse (fpo3) polarity selection when this bit is low, the output frame pul se fpo3 has the negative frame pulse format. when this bit is high, the output frame pul se fpo3 has the positive frame pulse format. 9fpo3pos output frame pulse (fpo3) position when this bit is low, fpo3 straddles frame boundary (as defined by st-bus). when this bit is high, fpo3 starts from frame boundary (as defined by gci-bus). 8cko2p output clock (cko2) polarity selection when this bit is low, the output clock cko2 falling edge aligns with the frame boundary. when this bit is high, the output clock cko2 rising edge aligns with the frame boundary. 7fpo2p output frame pulse (fpo2) polarity selection when this bit is low, the output frame pul se fpo2 has the negative frame pulse format. when this bit is high, the output frame pul se fpo2 has the positive frame pulse format. 6fpo2pos output frame pulse (fpo2) position when this bit is low, fpo2 straddles frame boundary (as defined by st-bus). when this bit is high, fpo2 starts from frame boundary (as defined by gci-bus). table 17 - output clock and frame pu lse selection register (ocfsr) bits external read/write address: 0004 h reset value: 0000 h 1514131211109876543210 00cko fpo3 sel1 cko fpo3 sel0 cko3 p fpo3 p fpo3 pos cko2 p fpo2 p fpo2 pos cko1 p fpo1 p fpo1 pos cko0 p fpo0 p fpo0 pos ckofpo3 sel1 - 0 fpo3 cko3 00 244 ns 4.096 mhz 01 122 ns 8.192 mhz 10 61 ns 16.384 mhz 11 30 ns 32.768 mhz
ZL50023 data sheet 41 zarlink semiconductor inc. 5cko1p output clock (cko1) polarity selection when this bit is low, the output clock cko1 falling edge aligns with the frame boundary. when this bit is high, the output clock cko1 rising edge aligns with the frame boundary. 4fpo1p output frame pulse (fpo1) polarity selection when this bit is low, the output frame pul se fpo1 has the negative frame pulse format. when this bit is high, the output frame pul se fpo1 has the positive frame pulse format. 3fpo1pos output frame pulse (fpo1) position when this bit is low, fpo1 straddles frame boundary (as defined by st-bus). when this bit is high, fpo1 starts from frame boundary (as defined by gci-bus). 2cko0p output clock (cko0) polarity selection when this bit is low, the output clock cko0 falling edge aligns with the frame boundary. when this bit is high, the output clock cko0 rising edge aligns with the frame boundary. 1fpo0p output frame pulse (fpo0) polarity selection when this bit is low, the output frame pul se fpo0 has the negative frame pulse format. when this bit is high, the output frame pul se fpo0 has the positive frame pulse format. 0fpo0pos output frame pulse (fpo0) position when this bit is low, fpo0 straddles frame boundary (as defined by st-bus). when this bit is high, fpo0 starts from frame boundary (as defined by gci-bus). note: in divided clock modes, cko3 - 1 cannot exceed frequency of cki. bit name description table 17 - output clock and frame pulse se lection register (ocfsr) bits (continued) external read/write address: 0004 h reset value: 0000 h 1514131211109876543210 00cko fpo3 sel1 cko fpo3 sel0 cko3 p fpo3 p fpo3 pos cko2 p fpo2 p fpo2 pos cko1 p fpo1 p fpo1 pos cko0 p fpo0 p fpo0 pos
ZL50023 data sheet 42 zarlink semiconductor inc. bit name description 15 - 10 unused reserved. in normal functional mode, these bits must be set to zero. 9 - 2 fof[n]off7 - 0 fpo_off[n] channel offset the binary value of these bits refers to the channel offset from original frame bound- ary. permitted channel offset values depend on bits 1-0 of this register. 1 - 0 fof[n]c1 - 0 fpo_off[n] control bits note: [n] denotes output offset frame pulse from 0 to 2. table 18 - fpo_off[n] register (fpo_off[n]) bits external read/write address: 0005 h - 0007 h reset value: 0000 h 1514131211109876543210 00000 0fof[n] off7 fof[n] off6 fof[n] off5 fof[n] off4 fof[n] off3 fof[n] off2 fof[n] off1 fof[n] off0 fof[n] c1 fof[n] c0 fof[n]c 1-0 data rate (mbps) fpo_off[n] pulse cycle width fof[n]off7 - 0 permitted channel offset polarity control position control 00 2.048 one 4.096 mhz clock 0 - 31 fpo0p fpo0pos 01 4.096 one 8.192 mhz clock 0 - 63 fpo1p fpo1pos 10 8.192 one 16.384 mhz clock 0 - 127 fpo2p fpo2pos 11 16.384 one 16.384 mhz clock 0 - 255 fpo2p fpo2pos
ZL50023 data sheet 43 zarlink semiconductor inc. bit name description 15 - 2 unused reserved in normal functional mode, these bits are zero. 1outerr output error (read only) this bit is set high when the total num ber of output channels is programmed to be more than the maximum capacity of 4096, in which case the output channels beyond the maximum capacity should be disabled. this bit will be cleared automatica lly after programming is corrected. 0inerr input error (read only) this bit is set high when the total number of input channels is programmed to be more than the maximum capacity of 4096, in which case the input channels beyond the maximum capacity should be di sabled.this bit will be clea red automatically after pro- gramming is corrected. table 19 - internal flag register (ifr) bits - read only bit name description 15 - 0 berf[n] ber error flag[n]: if berf[n] is high, it indicates that ber receiver error register [n] (brer[n]) is not zero. if berf[n] is low, it indicates that ber re ceiver error register [n] (brer[n]) is zero. note: [n] denotes input stream from 0 - 15. table 20 - ber error flag register 0 (berfr0) bits - read only external read address: 0010 h reset value: 0000 h 15141312111098765432 1 0 00000000000000out err in err external read address: 00011 h reset value: 0000 h 1514131211109876543210 ber f15 ber f14 ber f13 ber f12 ber f11 ber f10 ber f9 ber f8 ber f7 ber f6 ber f5 ber f4 ber f3 ber f2 ber f1 ber f0
ZL50023 data sheet 44 zarlink semiconductor inc. bit name description 15 - 0 berf[n] ber error flag[n]: if berf[n] is high, it indicates that ber receiver error register [n] (brer[n]) is not zero. if berf[n] is low, it indicates that ber re ceiver error register [n] (brer[n]) is zero. note: [n] denotes input stream from 16 - 31. table 21 - ber error flag register 1 (berfr1) bits - read only bit name description 15 - 0 berl[n] ber receiver lock[n] if berl[n] is high, it indicates that ber receiver of sti[n] is locked. if berl[n] is low, it indicates that ber receiver of sti[n] is not locked. note: [n] denotes input stream from 0 - 15. table 22 - ber receiver lock register 2 (berlr2) bits - read only external read/write address: 00012 h reset value: 0000 h 1514131211109876543210 ber f31 ber f30 ber f29 ber f28 ber f27 ber f26 ber f25 ber f24 ber f23 ber f22 ber f21 ber f20 ber f19 ber f18 ber f17 ber f16 external read address: 00013 h reset value: 0000 h 1514131211109876543210 ber l15 ber l14 ber l13 ber l12 ber l11 ber l10 ber l9 ber l8 ber l7 ber l6 ber l5 ber l4 ber l3 ber l2 ber l1 ber l0
ZL50023 data sheet 45 zarlink semiconductor inc. bit name description 15 - 0 berl[n] ber receiver lock[n]: if berl[n] is high, it indicates that ber receiver of sti[n] is locked. if berl[n] is low, it indicates that ber receiver of sti[n] is not locked. note: [n] denotes input stream from 16 - 31. table 23 - ber receiver lock register 3 (berlr3) bits - read only external read address: 00014 h reset value: 0000 h 1514131211109876543210 ber l31 ber l30 ber l29 ber l28 ber l27 ber l26 ber l25 ber l24 ber l23 ber l22 ber l21 ber l20 ber l19 ber l18 ber l17 ber l16
ZL50023 data sheet 46 zarlink semiconductor inc. bit name description 15 - 9 unused reserved in normal functional mode, these bits must be set to zero . 8 - 6 stin[n]bd2 - 0 input stream[n] bit delay bits. the binary value of these bits refers to the number of bits that the input stream will be delayed relative to fpi. the maxi mum value is 7. zero means no delay. 5 - 4 stin[n]smp1 - 0 input data sampling point selection bits 3 - 0 stin[n]dr3 - 0 input data rate selection bits: note: [n] denotes input stream from 0 - 31 . table 24 - stream input control register 0 - 31 (sicr0 - 31) bits external read/write address: 0100 h - 011f h reset value: 0000 h 1514131211109876543210 0000000stin[n] bd2 stin[n] bd1 stin[n] bd0 stin[n] smp1 stin[n] smp0 stin[n] dr3 stin[n] dr2 stin[n] dr1 stin[n] dr0 stin[n]smp1-0 sampling point (2.048 mbps, 4.096 mbps, 8.192 mbps streams) sampling point (16.384 mbps streams) 00 3/4 point 2/4 point 01 1/4 point 10 2/4 point 4/4 point 11 4/4 point stin[n]dr3-0 data rate 0000 stream unused 0001 2.048 mbps 0010 4.096 mbps 0011 8.192 mbps 0100 16.384 mbps 0101 - 1111 reserved
ZL50023 data sheet 47 zarlink semiconductor inc. bit name description 15 - 12 unused reserved in normal functional mode, these bits must be set to zero. 11 - 9 stin[n]q3c2 - 0 quadrant frame 3 control bits these three bits are used to control sti[ n]?s quadrant frame 3, which is defined as ch24 to 31, ch48 to 63, ch96 to 127 and ch192 to 255 for the 2.048 mbps, 4.096 mbps, 8.192 mbps, and 16.384 mbps modes respectively. 8 - 6 stin[n]q2c2 - 0 quadrant frame 2 control bits these three bits are used to control sti[ n]?s quadrant frame 2, which is defined as ch16 to 23, ch32 to 47, ch64 to 95 and ch128 to 191 for the 2.048 mbps, 4.096 mbps 8.192 mbps, and 16.384 mbps modes respectively. table 25 - stream input quadrant frame register 0 - 31 (siqfr0 - 31) bits external read/write address: 0120 h - 013f h reset value: 0000 h 1514131211109876543210 0000 stin[n] q3c2 stin[n] q3c1 stin[n] q3c0 stin[n] q2c2 stin[n] q2c1 stin[n] q2c0 stin[n] q1c2 stin[n] q1c1 stin[n] q1c0 stin[n] q0c2 stin[n] q0c1 stin[n] q0c0 stin[n]q3c 2-0 operation 0xx normal operation 100 lsb of each channel is replaced by ?0? 101 lsb of each channel is replaced by ?1? 110 msb of each channel is replaced by ?0? 111 msb of each channel is replaced by ?1? stin[n]q2c 2-0 operation 0xx normal operation 100 lsb of each channel is replaced by ?0? 101 lsb of each channel is replaced by ?1? 110 msb of each channel is replaced by ?0? 111 msb of each channel is replaced by ?1?
ZL50023 data sheet 48 zarlink semiconductor inc. 5 - 3 stin[n]q1c2 - 0 quadrant frame 1 control bits these three bits are used to control sti[ n]?s quadrant frame 1, which is defined as ch8 to 15, ch16 to 31, ch32 to 63 and ch64 to 127 for the 2.048 mbps, 4.096 mbps, 8.192 mbps, and 16.384 mbps modes respectively. 2 - 0 stin[n]q0c2 - 0 quadrant frame 0 control bits these three bits are used to control sti[ n]?s quadrant frame 0, which is defined as ch0 to 7, ch0 to 15, ch0 to 31 and ch0 to 63 for the 2.048 mbps, 4.096 mbps, 8.192 mbps, and 16.384 mbps modes respectively. note: [n] denotes input stream from 0 - 31 . bit name description table 25 - stream input quadrant frame regi ster 0 - 31 (siqfr0 - 31) bits (continued) external read/write address: 0120 h - 013f h reset value: 0000 h 1514131211109876543210 0000 stin[n] q3c2 stin[n] q3c1 stin[n] q3c0 stin[n] q2c2 stin[n] q2c1 stin[n] q2c0 stin[n] q1c2 stin[n] q1c1 stin[n] q1c0 stin[n] q0c2 stin[n] q0c1 stin[n] q0c0 stin[n]q1c 2-0 operation 0xx normal operation 100 lsb of each channel is replaced by ?0? 101 lsb of each channel is replaced by ?1? 110 msb of each channel is replaced by ?0? 111 msb of each channel is replaced by ?1? stin[n]q0c2-0 operation 0xx normal operation 100 lsb of each channel is replaced by ?0? 101 lsb of each channel is replaced by ?1? 110 msb of each channel is replaced by ?0? 111 msb of each channel is replaced by ?1?
ZL50023 data sheet 49 zarlink semiconductor inc. bit name description 15 - 12 unused reserved in normal functional mode, these bits must be set to zero. 11 - 9 stohz[n]a2 - 0 (valid only for stio0-15) stohz additional advancement bits 8 - 7 sto[n]fa1 - 0 output stream[n] fract ional advancement bits 6 - 4 sto[n]ad2 - 0 output stream[n] bit ad vancement selection bits the binary value of these bits refers to the number of bits that the output stream is to be advanced relative to fpo. the maximum value is 7. zero means no advancement. 3 - 0 sto[n]dr3 - 0 output data rate selection bits note: [n] denotes output stream from 0 - 31 . table 26 - stream output control register 0 - 31 (socr0 - 31) bits external read/write address: 0200 h - 021f h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 stohz [n]a2 stohz [n]a1 stohz [n]a0 sto[n] fa1 sto[n] fa0 sto[n] ad2 sto[n] ad1 sto[n] ad0 sto[n] dr3 sto[n] dr2 sto[n] dr1 sto[n] dr0 stohz[n]a2-0 additional advancement (2.048 mbps, 4.096 mbps, 8.192 mbps) additional advancement (16.384 mbps streams) 000 0 bit 0 bit 001 1/4 bit 2/4 bit 010 2/4 bit 4/4 bit 011 3/4 bit reserved 100 4/4 bit 101-111 reserved sto[n]fa1-0 advancement (2.048 mbps, 4.096 mbps, 8.192 mbps streams) advancement (16.384 mbps streams) 00 0 0 01 1/4 bit 2/4 10 2/4 bit reserved 11 3/4 bit stin[n]dr3 - 0 data rate 0000 disabled: stio hiz (stohz driven high) 0001 2.048 mbps 0010 4.096 mbps 0011 8.192 mbps 0100 16.384 mbps 0101 - 1111 reserved
ZL50023 data sheet 50 zarlink semiconductor inc. bit name description 15 - 8 unused reserved in normal functional mode, these bits must be set to zero. 7 - 0 st[n] brs7 - 0 stream[n] ber receive start bits the binary value of these bits refers to the input channel in which the ber data starts to be compared. note: [n] denotes input stream from 0 - 31 table 27 - ber receiver start register [n] (brsr[n]) bits bit name description 15 - 9 unused reserved in normal functional mode, these bits must be set to zero. 8 - 0 st[n] bl8 - 0 stream[n] ber length bits the binary value of these bits refers to the number of consecutive channels expected to receive the ber pattern. the maximum number of ber channels is 32, 64, 128 and 256 for the data rates of 2.048 mbps, 4.096 mbps, 8.192 mbps and 16.384 mbps respectively. the minimum number of ber cha nnels is 1. if these bits are set to zero, no ber test will be performed. note: [n] denotes input stream from 0 - 31 table 28 - ber receiver length register [n] (brlr[n]) bits external read/write address: 0300 h - 031f h reset value: 0000 h 1514131211109876543210 00000000st[n] brs7 st[n] brs6 st[n] brs5 st[n] brs4 st[n] brs3 st[n] brs2 st[n] brs1 st[n] brs0 external read/write address: 0320 h - 03f h reset value: 0000 h 1514131211109876543210 0000000st[n] bl8 st[n] bl7 st[n] bl6 st[n] bl5 st[n] bl4 st[n] bl3 st[n] bl2 st[n] bl1 st[n] bl0
ZL50023 data sheet 51 zarlink semiconductor inc. bit name description 15 - 2 unused reserved in normal functional mode, these bits must be set to zero. 1st[n] cber stream[n] bit error rate counter clear when this bit is high, it resets the internal bit error counter and the stream ber receiver error register to zero. 0st[n] sber stream[n] bit error rate test start when this bit is high, it enables the ber rece iver; starts the bit er ror rate test. the bit error test result is kept in the ber re ceiver error (brer[n]) register. upon the completion of the ber test, se t this bit to zero. note that the rbereb bit must be set in the ims register first. note: [n] denotes input stream from 0 - table 29 - ber receiver control register [n] (brcr[n]) bits bit name description 15 - 0 st[n] bc15 - 0 stream[n] ber count bits (read only) the binary value of these bits refers to the bit error counts. when it reaches its maxi- mum value of 0xffff, the value will be held and will not rollover. note: [n] denotes input stream from 0 - table 30 - ber receiver error register [n] (brer[n]) bits - read only external read/write address: 0340 h - 035f h reset value: 0000 h 15141312111098765432 1 0 00000000000000st[n] cber st[n] sber external read address: 0360 h - 037f h reset value: 0000 h 1514131211109876543210 st[n] bc15 st[n] bc14 st[n] bc13 st[n] bc12 st[n] bc11 st[n] bc10 st[n] bc9 st[n] bc8 st[n] bc7 st[n] bc6 st[n] bc5 st[n] bc4 st[n] bc3 st[n] bc2 st[n] bc1 st[n] bc0
ZL50023 data sheet 52 zarlink semiconductor inc. 20.0 memory 20.1 memory address mappings when a13 is high, the data or connection memory can be accessed by the microprocessor port. bit 1 - 0 in the control register determine the access to th e data or connection memory (cm_l or cm_h). msb (note 1) stream address (st0 - 31) channel address (ch0 - 255) a13 a12a11a10 a9 a8 stream [n] a7a6a5a4a3a2a1a0 channel [n] 1 1 1 1 1 1 1 1 1 . . . . . 1 1 . . . . 1 1 0 0 0 0 0 0 0 0 0 . . . . . 0 0 . . . . 1 1 0 0 0 0 0 0 0 0 1 . . . . . 1 1 . . . . 1 1 0 0 0 0 1 1 1 1 0 . . . . . 1 1 . . . . 1 1 0 0 1 1 0 0 1 1 0 . . . . . 1 1 . . . . 1 1 0 1 0 1 0 1 0 1 0 . . . . . 0 1 . . . . 0 1 stream 0 stream 1 stream 2 stream 3 stream 4 stream 5 stream 6 stream 7 stream 8 . . . . . stream 14 stream 15 . . . . stream 30 stream 31 0 0 . . 0 0 0 0 . . 0 0 . . . . 0 0 . . . . 1 1 0 0 . . 0 0 0 0 . . 0 0 . . . . 1 1 . . . . 1 1 0 0 . . 0 0 1 1 . . 1 1 . . . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 1 1 . . . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 . . 1 1 . . . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 . 1 1 . . . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 1 1 . . . . 1 1 . . . . 1 1 0 1 . . 0 1 0 1 . . 0 1 . . . . 0 1 . . . . 0 1 ch 0 ch 1 . . ch 30 ch 31 (note 2) ch 32 ch 33 . . ch 62 ch 63 (note 3) . . . . ch126 ch 127 (note 4) . . . . ch 254 ch 255 (note 5) note 1: a13 must be high for access to data and connection memory positions. a13 must be low to access internal registers. note 2: channels 0 to 31 are used when serial stream is at 2.048 mbps. note 3: channels 0 to 63 are used when serial stream is at 4.096 mbps. note 4: channels 0 to 127 are used when serial stream is at 8.192 mbps. note 5: channels 0 to 255 are used when serial stream is at 16.384 mbps. table 31 - address map for memory locations (a13 = 1)
ZL50023 data sheet 53 zarlink semiconductor inc. 20.2 connection memory low (cm_l) bit assignment when the cmm bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal channel-switching. the connection memory low bit assi gnment for the channel transmission mode is shown in table 32 on page 53. bit name description 15 uaen conversion between -law and a-law enable when this bit is low, normal switch without -law/a-law conversion. connec- tion memory high will be ignored. when this bit is high, switch with -law/a-law conversion, and connection memory high controls the conversion method. 14 v/c variable/constant delay control when this bit is low, the output data for this channel will be taken from con- stant delay memory. when this bit is set to high, the output data for this channel will be taken from variable delay memory. note that varen must be set in control register first. 13 - 9 ssa4 - 0 source stream address the binary value of these 5 bits re presents the input stream number. 8 - 1 sca7 - 0 source channel address the binary value of these 8 bits re presents the input channel number. 0 cmm = 0 connection memory mode = 0 if this is low, the connection memory is in the normal switching mode. bit13 - 1 are the source stream number and channel number. note: for proper - law/a-law conversion, the cm_h bits should be set before bit 15 (uaen bit) is set to high. table 32 - connection memory low (cm_l) bit assignment when cmm = 0 151413121110987654321 0 ua en v/c ssa 4 ssa 3 ssa 2 ssa 1 ssa 0 sca 7 sca 6 sca 5 sca 4 sca 3 sca 2 sca 1 sca 0 cmm =0
ZL50023 data sheet 54 zarlink semiconductor inc. when cmm is one, the device is programmed to perform one of the special per-channel transmission modes. bits pcc0 and pcc1 from connection memory are used to select the per-channel tristate, message or ber test mode as shown in table 33 on page 54. 20.3 connection memory high (cm_h) bit assignment connection memory high provides the detailed information required for -law and a-law conversion. icl and ocl bits describe the input coding law and the output coding law, respectively. they are used to select the expected pcm coding laws for the connection, on the tdm inputs, and on the tdm outputs. the v /d bit is used to select the class of coding law. if the v /d bit is cleared (to select a voice connection), the icl and ocl bits select between a-law and -law specifications related to g.711 voice coding. if the v /d bit is set (to select a data connection), the icl and ocl bits select between various bit inverting protoc ols. these coding laws are illustrated in the following table. if the icl is different than the ocl, all data bytes passing through the switch on th at particular connection are translated between the indicated laws. if the icl and the oc l are the same, no coding law translation is performed. the icl, the ocl bits and v /d bit only have an effect on pcm code tran slations for constant delay connections, variable delay connections and per-channel message mode. bit name description 15 uaen conversion between -law and a-law enable (message mode only) when this bit is low, message mode has no -law/a-law conversion. connec- tion memory high will be ignored. when this bit is high, message mode has -law/a-law conversion, and con- nection memory high controls the conversion method. 14 - 11 unused reserved in normal functional mode, these bits must be set to zero. 10 - 3 msg7 - 0 message data bits 8-bit data for the message mode. not used in the per-channel tristate and ber test modes. 2 - 1 pcc1 - 0 per-channel control bits these two bits control the correspondi ng entry?s value on the stio stream . 0 cmm = 1 connection memory mode = 1 if this is high, the connection memory is in the per-channel control mode which is per-channel tristate, per-channel message mode or per-channel ber mode. note: for proper - law/a-law conversion, the cm_h bits should be set before bit 15 (uaen bit) is set to high. table 33 - connection memory low (cm_l) bit assignment when cmm = 1 151413121110987654321 0 ua en 0000msg 7 msg 6 msg 5 msg 4 msg 3 msg 2 msg 1 msg 0 pcc 1 pcc 0 cmm =1 pc c1 pc c0 channel output mode 0 0 per channel tristate 0 1 message mode 10 ber test mode 11 reserved
ZL50023 data sheet 55 zarlink semiconductor inc. bit name description 15 - 5 unused reserved in normal functional mode, these bits must be set to zero. 4v /d voice/data control when this bit is low, the corresponding channel is for voice. when this bit is high, the corresponding channel is for data. 3 - 2 icl1 - 0 input coding law. 1 - 0 ocl1 - 0 output coding law note 1: for proper - law/a-law conversion, the cm_h bits should be set before bit 15 of cm_l is set to high. note 2: refer to g.711 standard for detail information of different laws. table 34 - connection memory high (cm_h) bit assignment 151413121110987654321 0 00000000000v /d icl 1 icl 0 ocl 1 ocl 0 icl1-0 input coding law for voice (v /d bit = 0) for data (v /d bit = 1) 00 ccitt.itu a-law no code 01 ccitt.itu -law abi 10 a-law w/o abi inverted abi 11 -law w/o magnitude inversion all bits inverted ocl1-0 output coding law for voice (v /d bit = 0) for data (v /d bit = 1) 00 ccitt.itu a-law no code 01 ccitt.itu -law abi 10 a-law w/o abi inverted abi 11 -law w/o magnitude inversion all bits inverted
ZL50023 data sheet 56 zarlink semiconductor inc. 21.0 dc parameters * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. * note 1: maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage ( v in ). absolute maximum ratings* parameter symbol min. max. units 1 i/o supply voltage v dd_io -0.5 5.0 v 2 core supply voltage v dd_core -0.5 2.5 v 3 input voltage v i_3v -0.5 v dd + 0.5 v 4 input voltage (5 v-tolerant inputs) v i_5v -0.5 7.0 v 5 continuous current at digital outputs i o 15 ma 6 package power dissipation p d 1.5 w 7 storage temperature t s - 55 +125 c recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated . characteristics sym. min. typ. ? max. units 1 operating temperature t op -40 25 +85 c 2 positive supply v dd_io 3.0 3.3 3.6 v 3 positive supply v dd_core 1.71 1.8 1.89 v 4 input voltage v i 03.3v dd_io v 5 input voltage on 5 v-tolerant inputs v i_5v 05.05.5v dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 supply current - v dd_core i dd_core 130 ma 2 supply current - v dd_io i dd_io 70 ma c l =30pf 3 input high voltage v ih 2.0 v 4 input low voltage v il 0.8 v 5 input leakage (input pins) input leakage (bi-di rectional pins) i il i bl 5 5 a a 0 ZL50023 data sheet 57 zarlink semiconductor inc. 22.0 ac parameters ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. figure 19 - timing parameter measurement voltage levels ac electrical characteristics ? - timing parameter measurement voltage levels characteristics sym. level units conditions 1 cmos threshold v ct 0.5 v dd_io v 2 rise/fall threshold voltage high v hm 0.7 v dd_io v 3 rise/fall threshold voltage low v lm 0.3 v dd_io v timing reference points all signals v hm v ct v lm
ZL50023 data sheet 58 zarlink semiconductor inc. figure 20 - motorola non-multiplexed bus timing - read access ac electrical characteristics - motorola non-multiplexed bus mode - read access characteristics sym min. typ. ? max. units test conditions 2 1cs de-asserted time t csd 15 ns 2ds de-asserted time t dsd 15 ns 3cs setup to ds falling t css 0ns 4r/w setup to ds falling t rws 10 ns 5 address setup to ds falling t as 5ns 6cs hold after ds rising t csh 0ns 7r/w hold after ds rising t rwh 0ns 8 address hold after ds rising t ah 0ns 9 data setup to dta low t ds 8nsc l = 50 pf 10 data hold after ds rising t dhz 8nsc l = 50 pf, r l = 1 k (note 1) 11 acknowledgement delay time. from ds low to dta low: registers memory t akd 75 185 ns ns c l = 50 pf c l = 50 pf 12 acknowledgement hold time. from ds high to dta high t akh 412nsc l = 50 pf, r l = 1 k (note 1) 13 dta drive high to hiz t akz 8ns note 1: high impedance is measured by pulling to th e appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (see section 13.2 on page 30) must be applied before the first microprocessor access is performed after the reset pin is set high. ds a0-a13 d0-d15 t csh t ah t rws r/w t as t rwh t akd t ds t akh dta v ct v ct v ct v ct v ct v ct valid address valid read data t css t dsd cs t akz t csd t dhz
ZL50023 data sheet 59 zarlink semiconductor inc. figure 21 - motorola non-multiplexed bus timing - write access ac electrical characteristics - motorola non-multiplexed bus mode - write access characteristics sym. min. typ. ? max. units test conditions 2 1cs de-asserted time t csd 15 ns 2ds de-asserted time t dsd 15 ns 3cs setup to ds falling t css 0ns 4r/w setup to ds falling t rws 10 ns 5 address setup to ds falling t as 5ns 6 data setup to ds falling t ds 0nsc l = 50 pf 7cs hold after ds rising t csh 0ns 8r/w hold after ds rising t rwh 0ns 9 address hold after ds rising t ah 0ns 10 data hold from ds rising t dh 5nsc l = 50 pf, r l = 1k (note 1) 11 acknowledgement delay time. from ds low to dta low: registers memory t akd 55 150 ns ns c l = 50 pf c l = 50 pf 12 acknowledgement hold time. from ds high to dta high t akh 412nsc l = 50 pf, r l = 1k (note 1) 13 dta drive high to hiz t akz 8ns note 1: high impedance is measured by pulling to th e appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (see section 13.2 on page 30) must be applied before the first microprocessor access is performed after the reset pin is set high. ds a0-a13 t csh t ah t rws r/w t as t rwh t akd t akh dta v ct v ct v ct v ct v ct t css t dsd cs t akz d0-d15 t dh t ds v ct valid write data t csd valid address
ZL50023 data sheet 60 zarlink semiconductor inc. figure 22 - intel non-multiplexed bus timing - read access ac electrical characteristics - intel non-multiplexed bus mode - read access characteristics sym. min. typ. ? max. units test conditions 2 1cs de-asserted time t csd 15 ns 2rd setup to cs falling t rs 10 ns 3wr setup to cs falling t ws 10 ns 4 address setup to cs falling t as 5ns 5rd hold after cs rising t rh 0ns 6wr hold after cs rising t wh 0ns 7 address hold after cs rising t ah 0ns 8 data setup to rdy high t ds 8nsc l = 50 pf 9 data hold after cs rising t csz 7nsc l = 50 pf, r l = 1 k (note 1) 10 acknowledgement delay time. from cs low to rdy high: registers memory t akd 175 185 ns ns c l = 50 pf c l = 50 pf 11 acknowledgement hold time. from cs high to rdy low t akh 412nsc l = 50 pf, r l = 1 k (note 1) 12 rdy drive low to hiz t akz 8ns note 1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (see section 13.2 on page 30) must be applied before the first microprocessor access is performed after the reset pin is set high. cs a0-a13 d0-d15 t ah t ws wr t wh t akd t ds t akh rdy v ct v ct v ct v ct v ct valid address valid read data t csd t akz t rs rd t rh v ct t as t csz
ZL50023 data sheet 61 zarlink semiconductor inc. figure 23 - intel non-multiple xed bus timing - write access ac electrical characteristics - intel non-multiplexed bus mode - write access characteristics sym. min. typ. ? max. units test conditions 2 1cs de-asserted time t csd 15 ns 2wr setup to cs falling t ws 10 ns 3rd setup to cs falling t rs 10 ns 4 address setup to cs falling t as 5ns 5 data setup to cs falling t ds 0nsc l = 50 pf 6wr hold after cs rising t wh 0ns 7rd hold after cs rising t rh 0ns 8 address hold after cs rising t ah 10 ns 9 data hold after cs rising t dh 5nsc l = 50 pf, r l = 1k (note 1) 10 acknowledgement delay time. from cs low to rdy high: registers memory t akd 55 150 ns ns c l = 50 pf c l = 50 pf 11 acknowledgement hold time. from cs high to rdy low t akh 412nsc l = 50 pf, r l = 1k (note 1) 12 rdy drive low to hiz t akz 8ns note 1: high impedance is measured by pulling to th e appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (section 13.2 on page 30) must be applied before the first microprocessor access is performed after the reset pin is set high. cs a0-a13 d0-d15 t ah t rs rd t rh t akd t akh rdy v ct v ct v ct v ct v ct valid address t csd t akz t ws wr t wh v ct t as valid write data t ds t dh
ZL50023 data sheet 62 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. figure 24 - jtag test port timing diagram ac electrical characteristics ? - jtag test port timing characteristic sym. min. typ. ? max. units notes 1 tck clock period t tckp 100 ns 2 tck clock pulse width high t tckh 20 ns 3 tck clock pulse width low t tckl 20 ns 4 tms set-up time t tmss 10 ns 5 tms hold time t tmsh 10 ns 6 tdi input set-up time t tdis 20 ns 7 tdi input hold time t tdih 60 ns 8 tdo output delay t tdod 30 ns c l = 30 pf 9trst pulse width t trstw 200 ns t tmsh t tmss t tckl t tckh t tckp t tdis t tdih t tdod t trstw tms tck tdi tdo trst
ZL50023 data sheet 63 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ac electrical characteristics ? - fpi and cki timing when ckin1-0 bits = 00 (16.384 mhz) characteristic sym. min. typ. ? max. units notes 1 fpi input frame pulse width t fpiw 40 61 115 ns 2 fpi input frame pulse setup time t fpis 20 ns 3 fpi input frame pulse hold time t fpih 20 ns 4 cki input clock period t ckip 55 61 67 ns 5 cki input clock high time t ckih 27 34 ns 6 cki input clock low time t ckil 27 34 ns 7 cki input clock rise/fall time t r cki, t f cki 3 ns 8 cki input clock cycle to cycle variation t cvc 020ns ac electrical characteristics ? - fpi and cki timing when ckin1-0 bits = 01 (8.192 mhz) characteristic sym. min. typ. ? max. units notes 1 fpi input frame pulse width t fpiw 90 122 220 ns 2 fpi input frame pulse setup time t fpis 45 ns 3 fpi input frame pulse hold time t fpih 45 ns 4 cki input clock period t ckip 110 122 135 ns 5 cki input clock high time t ckih 55 69 ns 6 cki input clock low time t ckil 55 69 ns 7 cki input clock rise/fall time t r cki, t f cki 3 ns 8 cki input clock cycle to cycle variation t cvc 020ns ac electrical characteristics - fpi and cki timing when ckin1-0 bits = 10 (4.096 mhz) characteristic sym. min. typ. ? max. units notes 1 fpi input frame pulse width t fpiw 90 244 420 ns 2 fpi input frame pulse setup time t fpis 110 ns 3 fpi input frame pulse hold time t fpih 110 ns 4 cki input clock period t ckip 220 244 270 ns 5 cki input clock high time t ckih 110 135 ns 6 cki input clock low time t ckil 110 135 ns 7 cki input clock rise/fall time t r cki, t f cki 3 ns 8 cki input clock cycle to cycle variation t cvc 020ns
ZL50023 data sheet 64 zarlink semiconductor inc. figure 25 - frame pulse input and clock input timing diagram (st-bus) figure 26 - frame pulse input and clock input timing diagram (gci-bus) t fpiw fpi t fpih t ckih t ckil t fpis t ckip cki input frame boundary t rcki t fcki t fpiw fpi t fpih t ckih t ckil t fpis t ckip cki input frame boundary t rcki t fcki
ZL50023 data sheet 65 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. figure 27 - st-bus input timing diagram when operated at 2 mbps, 4 mbps, 8 mbps ac electrical characteristics ? - st-bus/gci-bus input timing characteristic sym. min. typ. ? max. units test conditions 1 sti setup time 2.048 mbps 4.096 mbps 8.192 mbps 16.384 mbps t sis2 t sis4 t sis8 t sis16 5 5 5 5 ns ns ns ns 2sti hold time 2.048 mbps 4.096 mbps 8.192 mbps 16.384 mbps t sih2 t sih4 t sih8 t sih16 8 8 8 8 ns ns ns ns v tt cki fpi (16.384 mhz) cki fpi (8.192 mhz) cki fpi (4.096 mhz) t sis2 t sih2 bit7 ch0 bit6 ch0 t sis4 t sih4 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit0 ch63 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit0 ch0 bit1 ch127 8.192 mbps 4.096 mbps 2.048 mbps t sis8 t sih8 sti0 - 31 sti0 - 31 sti0 - 31 v ct v ct bit0 ch31 v ct input frame boundary bit0 ch127
ZL50023 data sheet 66 zarlink semiconductor inc. figure 28 - st-bus input timing diagram when operated at 16 mbps figure 29 - gci-bus input timing diagram wh en operated at 2 mbps, 4 mbps, 8 mbps v tt cki fpi (16.384 mhz) bit0 ch255 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit0 ch0 bit1 ch255 16.384 mbps t sis16 t sih16 input frame boundary sti0 - 31 v ct bit7 ch0 v tt cki fpi (16.384 mhz) cki fpi (8.192 mhz) cki fpi (4.096 mhz) t sis2 t sih2 bit0 ch0 bit1 ch0 t sis4 t sih4 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit7 ch63 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit6 ch127 8.192 mbps 4.096 mbps 2.048 mbps t sis8 t sih8 sti0 - 31 sti0 - 31 sti0 - 31 v ct v ct bit7 ch31 v ct input frame boundary bit7 ch127
ZL50023 data sheet 67 zarlink semiconductor inc. figure 30 - gci-bus input timing diagram when operated at 16 mbps v tt cki fpi (16.384 mhz) bit7 ch255 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit6 ch255 16.384 mbps t sis16 t sih16 input frame boundary sti0 - 31 v ct bit0 ch0
ZL50023 data sheet 68 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. figure 31 - st-bus output timing diagra m when operated at 2, 4, 8 or 16 mbps ac electrical characteristics ? - st-bus/gci-bus output timing characteristic sym. min. typ. ? max. units test conditions 1 stio delay - active to active @2.048 mbps @4.096 mbps @8.192 mbps @16.384 mbps @2.048 mbps @4.096 mbps @8.192 mbps @16.384 mbps t sod2 t sod4 t sod8 t sod16 t sod2 t sod4 t sod8 t sod16 0 0 0 0 -6 -6 -6 -6 6 6 6 6 0 0 0 0 ns ns ns ns ns ns ns ns c l = 30 pf multiplied clock mode divided clock mode bit0 ch255 cko0 fpo0 (4.096 mhz) 8.192 mbps 4.096 mbps 2.048 mbps output frame boundary stio0 - 15 stio0 - 15 stio0 - 15 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit0 ch63 bit7 ch0 bit6 ch0 bit0 ch31 t sod2 t sod4 t sod8 v ct v ct v ct bit0 ch127 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit0 ch0 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch255 bit1 ch255 bit2 ch0 bit1 ch0 bit0 ch0 bit7 ch1 bit6 ch1 bit5 ch1 bit4 ch1 bit3 ch1 bit2 ch1 bit1 ch1 v ct t sod16 16.384 mbps stio0 - 15
ZL50023 data sheet 69 zarlink semiconductor inc. figure 32 - gci-bus output timing diagram when operated at 2, 4, 8 or 16 mbps cko0 fpo0 (4.096 mhz) output frame boundary bit7 ch255 8.192 mbps 4.096 mbps 2.048 mbps stio0 - 15 stio0 - 15 stio0 - 15 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit7 ch63 bit0 ch0 bit1 ch0 bit7 ch31 t sod2 t sod4 t sod8 v ct v ct v ct bit7 ch127 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch255 bit6 ch255 bit5 ch0 bit6 ch0 bit7 ch0 bit0 ch1 bit1 ch1 bit2 ch1 bit3 ch1 bit4 ch1 bit5 ch1 bit6 ch1 v ct t sod16 16.384 mbps stio0 - 15
ZL50023 data sheet 70 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. * test condition is r l = 1 k, c l = 30 pf; high impedance is measured by pulling to the app ropriate rail with r l , with timing corrected to cancel the time taken to discharge c l . figure 33 - serial output and external control figure 34 - output drive enable (ode) ac electrical characteristics ? - st-bus/gci-bus output tristate timing characteristic sym. min. typ. ? max. units test conditions * 1 stio delay - active to high-z t dz -3 -8 7 0 ns ns multiplied clock mode divided clock mode 2 stio delay - high-z to active t zd -3 -8 7 0 ns ns multiplied clock mode divided clock mode 3 output drive enable (ode) delay - high-z to active cki @ 4.096mhz cki @ 8.192mhz cki @ 16.384mhz t zd_ode 77 260 138 77 ns ns ns ns multiplied clock mode divided clock mode 4 output drive enable (ode) delay - active to high-z cki @ 4.096mhz cki @ 8.192mhz cki @ 16.384mhz t dz_ode 77 260 138 77 nsns ns ns multiplied clock mode divided clock mode t dz stio t zd stio cko0 v ct v ct tristate valid data v ct tristate valid data fpo0 v ct hiz hiz stio ode t zd_ode valid data t dz_ode v ct v ct
ZL50023 data sheet 71 zarlink semiconductor inc. ac electrical ch aracteristics - input/output frame boundary alignment figure 35 - input and out put frame boundary offset characteristic sym. min. typ. ? max. units notes 1 input and output frame offset in divided clock mode t fbos 513ns 2 input and output frame offset in multiplied clock mode t fbos 2 10 ns input reference jitter is equal to zero. cki fpi (16.384 mhz) cki fpi (8.192 mhz) cki fpi (4.096 mhz) input frame boundary cko0 fpo0 (4.096 mhz) output frame boundary t fbos
ZL50023 data sheet 72 zarlink semiconductor inc. figure 36 - fpo0/3 and cko0/3 timing diagram ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ac electrical ch aracteristics ? - fpo0/cko0 and fpo3/cko3 (4.096 mhz) timing for multiplied clock mode with more than 10 ns of cycle to cycle variation on cki ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ac electrical characteristics ? - fpo0/cko0 and fpo3/cko3 (4.096 mhz) timing for divided clock mode and multiplied clock mode with less than 10 ns of cycle to cycle variation on cki characteristic sym. min. typ. ? max. units notes 1 fpo0 output pulse width t fpw03 239 244 249 ns c l = 30 pf 2 fpo0 output delay from the fpo0 falling edge to the output frame boundary t fodf03 117 127 ns 3 fpo0 output delay from the output frame boundary to the fpo0 rising edge t fodr03 117 127 ns 4 cko0 output clock period t ckp03 239 244 249 ns c l = 30 pf 5 cko0 output high time t ckh03 117 127 ns 6 cko0 output low time t ckl03 117 127 ns 7 cko0 output rise/fall time t rck03 , t fck03 5ns characteristic sym. min. typ. ? max. units notes 1 fpo0 output pulse width t fpw03 218 244 270 ns c l = 30 pf 2 fpo0 output delay from the fpo0 falling edge to the output frame boundary t fodf03 117 127 ns 3 fpo0 output delay from the output frame boundary to the fpo0 rising edge t fodr03 97 146 ns 4 cko0 output clock period t ckp03 218 244 270 ns c l = 30 pf 5 cko0 output high time t ckh03 117 127 ns 6 cko0 output low time t ckl03 97 146 ns 7 cko0 output rise/fall time t rck03 , t fck03 5ns t fpw03 t fodr03 t fodf03 fpo0/3 cko0/3 t ckl03 t ckh03 t ckp03 t rck03 t fck03 output frame boundary v ct v ct
ZL50023 data sheet 73 zarlink semiconductor inc. figure 37 - fpo1/3 and cko1/3 timing diagram ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ac electrical ch aracteristics ? - fpo1/cko1 and fpo3/cko3 (8.192 mhz) timing for multiplied clock mode with more than 10 ns of cycle to cycle variation on cki ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ac electrical characteristics ? - fpo1/cko1 and fpo3/cko3 (8.192 mhz) timing for divided clock mode and multiplied clock mode with less than 10 ns of cycle to cycle variation on cki characteristic sym. min. typ. ? max. units notes 1 fpo1 output pulse width t fpw13 117 122 127 ns c l = 30 pf 2 fpo1 output delay from the fpo1 falling edge to the output frame boundary t fodf13 56 66 ns 3 fpo1 output delay from the output frame boundary to the fpo1 rising edge t fodr13 56 66 ns 4 cko1 output clock period t ckp13 117 122 127 ns c l = 30 pf 5 cko1 output high time t ckh13 56 66 ns 6 cko1 output low time t ckl13 56 66 ns 7 cko1 output rise/fall time t rck13 , t fck13 5ns characteristic sym. min. typ. ? max. units notes 1 fpo1 output pulse width t fpw13 106 122 127 ns c l = 30 pf 2 fpo1 output delay from the fpo1 falling edge to the output frame boundary t fodf13 56 66 ns 3 fpo1 output delay from the output frame boundary to the fpo1 rising edge t fodr13 46 66 ns 4 cko1 output clock period t ckp13 106 122 148 ns c l = 30 pf 5 cko1 output high time t ckh13 46 87 ns 6 cko1 output low time t ckl13 46 66 ns 7 cko1 output rise/fall time t rck13 , t fck13 5ns t fpw13 t fodr13 t fodf13 fpo1/3 cko1/3 t ckl13 t ckh13 t ckp13 t rck13 t fck13 output frame boundary v ct v ct
ZL50023 data sheet 74 zarlink semiconductor inc. figure 38 - fpo2/3 and cko2/3 timing diagram ac electrical ch aracteristics ? - fpo2/cko2 and fpo3/cko3 (16.384 mhz) timing for divided clock mode and multiplied clock mode with less than 10 ns of cycle to cycle variation on cki ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ac electrical ch aracteristics ? - fpo2/cko2 and fpo3/cko3 (16.384 mhz) timing for multiplied clock mode with more than 10 ns of cycle to cycle variation on cki ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. characteristic sym. min. typ. ? max. units notes 1 fpo2 output pulse width t fpw23 56 61 66 ns c l = 30 pf 2 fpo2 output delay from the fpo1 falling edge to the output frame boundary t fodf23 25 36 ns 3 fpo2 output delay from the output frame boundary to the fpo1 rising edge t fodr23 25 36 ns 4 cko2 output clock period t ckp23 56 61 66 ns c l = 30 pf 5 cko2 output high time t ckh23 25 36 ns 6 cko2 output low time t ckl23 25 36 ns 7 cko2 output rise/fall time t rck23 , t fck23 5ns characteristic sym. min. typ. ? max. units notes 1 fpo2 output pulse width t fpw23 56 61 66 ns c l = 30 pf 2 fpo2 output delay from the fpo2 falling edge to the output frame boundary t fodf23 25 36 ns 3 fpo2 output delay from the output frame boundary to the fpo1 rising edge t fodr23 25 36 ns 4 cko2 output clock period t ckp2 47 61 76 ns c l = 30 pf 5 cko2 output high time t ckh23 17 43 ns 6 cko2 output low time t ckl23 17 43 ns 7 cko2output rise/fall time t rck23 , t fck23 5ns t fpw23 t fodr23 t fodf23 fpo2/3 cko2/3 t ckl23 t ckh23 t ckp23 t rck23 t fck23 output frame boundary v ct v ct
ZL50023 data sheet 75 zarlink semiconductor inc. figure 39 - fpo3 and cko3 timing diagram (32.768 mhz) ac electrical ch aracteristics ? - fpo3/cko3 (32.768 mhz) timing for divided clock mode and multiplied clock mode with less than 10 ns of cycle to cycle variation on cki ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ac electrical ch aracteristics ? - fpo3/cko3 (32.768 mhz) timing for mult iplied clock mode with more than 10 ns of cycle to cycle variation on cki ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. characteristic sym. min. typ. ? max. units notes 1 fpo3 output pulse width t fpw3 27 30.5 34 ns c l = 30 pf 2 fpo3 output delay from the fpo1 falling edge to the output frame boundary t fodf3 10 18 ns 3 fpo3 output delay from the output frame boundary to the fpo3 rising edge t fodr3 12 21 ns 4 cko3 output clock period t ckp3 27 30.5 34 ns c l = 30 pf 5 cko3 output high time t ckh3 12 19 ns 6 cko3 output low time t ckl3 12 19 ns 7 cko3 output rise/fall time t rck3 , t fck3 5ns characteristic sym. min. typ. ? max. units notes 1 fpo3 output pulse width t fpw3 27 30.5 34 ns c l = 30 pf 2 fpo3 output delay from the fpo1 falling edge to the output frame boundary t fodf3 12 19 ns 3 fpo3 output delay from the output frame boundary to the fpo1 rising edge t fodr3 12 19 ns 4 cko3 output clock period t ckp3 17 30.5 44 ns c l = 30 pf 5 cko3 output high time t ckh3 529ns 6 cko3 output low time t ckl3 12 18 ns 7 cko3 output rise/fall time t rck3 , t fck3 5ns t fpw3 t fodr3 t fodf3 fpo3 cko3 t ckl3 t ckh3 t ckp3 t rck3 t fck3 output frame boundary v ct v ct
ZL50023 data sheet 76 zarlink semiconductor inc. ac electrical ch aracteristics ? - divided clock mode output timing ac electrical ch aracteristics ? - multiplied clock mode output timing figure 40 - output timing (st-bus format) characteristic sym min max units 1 cko0 to cko1 (8.192 mhz) delay t c1d -1 2 ns 2 cko0 to cko2 (16.384 mhz) delay t c2d -1 3 ns 3 cko0 to cko3 (16.384 mhz/8.192 mhz/4.096 mhz) delay t c3d -2 2 ns characteristic sym min max units 1 cko0 to cko1 (8.192 mhz) delay t c1d -1 2 ns 2 cko0 to cko2 (16.384 mhz) delay t c2d -1 3 ns 3 cko0 to cko3 (32.768 mhz/16.384 mhz/8.192 mhz/4.096 mhz) delay t c3d -1 3 ns fpo0 cko1 cko0 v ct cko2 cko3 v ct v ct v ct t c1d t c2d t c3d (4.096 mhz) (8.192 mhz) (16.384 mhz) (32.768 mhz) v ct
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes b 214440 1 26june03
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes
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